CS5336 datasheet(12/34 Pages) CIRRUS

12 / 34 page

with the ADC straddling the boundary. All sig-

nals, especially clocks, should be kept away from

the VREF pin in order to avoid unwanted cou-

pling into the modulators. The VREF decoupling

capacitors, particularly the 0.1

µF, must be posi-

tioned to minimize the electrical path from VREF

to Pin 1 AGND and to minimize the path between

VREF and the capacitors. An evaluation board is

available which demonstrates the optimum layout

and power supply arrangements, as well as allow-

ing fast evaluation of the ADC.

To minimize digital noise, connect the ADC digi-

tal outputs only to CMOS inputs.

Synchronization of Multiple CS5336/8/9

In systems where multiple ADC’s are required,

care must be taken to insure that the ADC internal

clocks are synchronized between converters to in-

sure simultaneous sampling. In the absence of this

synchronization, the sampling difference could be

one ICLKD period which is typically 81.4 nsec

for a 48 kHz sample rate.

SLAVE MODE

Synchronous sampling in the slave mode is

achieved by connecting all DPD and APD pins to

a single control signal and supplying the same

ICLKD and L/R to all converters.

MASTER MODE

The internal counters of the CS5336/8/9 are reset

during DPD/APD high and will start simultane-

ously by insuring that the release of DPD/APD

for all converters is internally latched on the same

rising edge of ICLKD. This can be achieved by

connecting all DPD/APD pins to

the same

control signal and insuring that the DPD/APD

falling edge occurs outside a

±30 ns window

either side of an ICLKD rising edge.

PERFORMANCE

FFT Tests

For FFT based tests, a very pure sine wave is pre-

sented to the ADC, and an FFT analysis is

performed on the output data. The resulting spec-

trum is a measure of the performance of the ADC.

Figure 7 shows the spectral purity of the CS5336

with a 1 kHz, -10 dB input. Notice the low noise

floor, the absence of any harmonic distortion, and

the Dynamic Range value of 95.41 dB.

Figure 8 shows the CS5336 high frequency per-

formance. The input signal is a -10 dB, 9 kHz

sine wave. Notice the small 2nd harmonic at

110 dB down.

Figure 9 shows the low-level performance of the

CS5336. Notice the lack of any distortion compo-

nents. Traditional R-2R ladder based ADC’s can

have problems with this test, since differential

non-linearities around the zero point become very

significant. Figure 10 shows the same very low

input amplitude performance, but at 9kHz input

frequency.

CS5336, CS5338, CS5339

3-50

DS23F1

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