CS5336 datasheet(19/34 Pages) CIRRUS

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L/R - Left/Right Select, PIN 14.

In master mode (SMODE high), L/R is an output whose frequency is at the output word

rate. L/R edges occur 1 SCLK cycle before FSYNC rises. When L/R is high, left channel

data is on SDATA, except for the first SCLK cycle. When L/R is low, right channel data is

on SDATA, except for the first SCLK cycle. The MSB data bit appears on SDATA one

SCLK cycle after L/R changes.

In slave mode (SMODE low), L/R is an input which selects the left or right channel for

output on SDATA. The rising edge of L/R starts the MSB of the left channel data. L/R

frequency must be equal to the output word rate.

Although the outputs of each channel are transmitted at different times, the two words in

an L/R cycle represent simultaneously sampled analog inputs.

FSYNC - Frame Synchronization Signal, PIN 17.

In master mode (SMODE high), FSYNC is an output which goes high coincident with the

start of the first SDATA bit (MSB) and falls low immediately after the last SDATA audio

data bit (LSB).

In slave mode (SMODE low), FSYNC is an input which controls the clocking out of the

data bits on SDATA. FSYNC is normally tied high, which causes the data bits to be

clocked out immediately following L/R transitions. If it is desired to delay the data bits

from the L/R edge, then FSYNC must be low during the delay period. Bringing FSYNC

high will then enable the clocking out of the SDATA bits. Note that the MSB will be

clocked out based on the L/R edge, independent of the state of FSYNC.

Miscellaneous

NC - No Connection, PINS 8, 22.

These two pins are bonded out to test outputs. They must not be connected to any external

component or any length of PC trace.

TST -Test Input, PIN 11.

Allows access to the ADC test modes, which are reserved for factory use. Must be tied to

DGND.

CS5336, CS5338, CS5339

DS23F1

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CS5336 Datasheet(PDF) 19 Page - Cirrus Logic