PI7C7300D datasheet(5/107 Pages) PERICOM

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PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 5 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

TABLE OF CONTENTS

INTRODUCTION ............................................................................................................................ 11

BLOCK DIAGRAM......................................................................................................................... 12

SIGNAL DEFINITIONS ................................................................................................................. 13

3.1

SIGNAL TYPES ........................................................................................................................ 13

3.2

PRIMARY BUS INTERFACE SIGNALS ................................................................................ 13

3.3

SECONDARY BUS INTERFACE SIGNALS .......................................................................... 15

3.4

CLOCK SIGNALS..................................................................................................................... 17

3.5

MISCELLANEOUS SIGNALS ................................................................................................. 17

3.6

COMPACT PCI HOT-SWAP SIGNALS .................................................................................. 17

3.7

JTAG BOUNDARY SCAN SIGNALS ..................................................................................... 18

3.8

POWER AND GROUND .......................................................................................................... 18

3.9

PI7C7300D PBGA PIN LIST .................................................................................................... 18

PCI BUS OPERATION ................................................................................................................... 21

4.1

TYPES OF TRANSACTIONS .................................................................................................. 21

4.2

SINGLE ADDRESS PHASE ..................................................................................................... 22

4.3

DUAL ADDRESS PHASE ........................................................................................................ 22

4.4

DEVICE SELECT (DEVSEL#) GENERATION ...................................................................... 23

4.5

DATA PHASE ........................................................................................................................... 23

4.6

WRITE TRANSACTIONS ........................................................................................................ 23

4.6.1

MEMORY WRITE TRANSACTIONS.................................................................................. 24

4.6.2

MEMORY WRITE AND INVALIDATE TRANSACTIONS.................................................. 25

4.6.3

DELAYED WRITE TRANSACTIONS ................................................................................. 25

4.6.4

WRITE TRANSACTION ADDRESS BOUNDARIES .......................................................... 26

4.6.5

BUFFERING MULTIPLE WRITE TRANSACTIONS......................................................... 26

4.6.6

FAST BACK-TO-BACK WRITE TRANSACTIONS ............................................................ 27

4.7

READ TRANSACTIONS.......................................................................................................... 27

4.7.1

PREFETCHABLE READ TRANSACTIONS....................................................................... 27

4.7.2

NON-PREFETCHABLE READ TRANSACTIONS ............................................................. 27

4.7.3

READ PREFETCH ADDRESS BOUNDARIES.................................................................. 28

4.7.4

DELAYED READ REQUESTS ........................................................................................... 30

4.7.5

DELAYED READ COMPLETION WITH TARGET ........................................................... 30

4.7.6

DELAYED READ COMPLETION ON INITIATOR BUS................................................... 32

4.7.7

FAST BACK-TO-BACK READ TRANSACTION................................................................ 32

4.8

CONFIGURATION TRANSACTIONS.................................................................................... 33

4.8.1

TYPE 0 ACCESS TO PI7C7300D ...................................................................................... 33

4.8.2

TYPE 1 TO TYPE 0 CONVERSION ................................................................................... 34

4.8.3

TYPE 1 TO TYPE 1 FORWARDING.................................................................................. 35

4.8.4

SPECIAL CYCLES ............................................................................................................. 36

4.9

TRANSACTION TERMINATION ........................................................................................... 37

4.9.1

MASTER TERMINATION INITIATED BY PI7C7300D..................................................... 37

4.9.2

MASTER ABORT RECEIVED BY PI7C7300D.................................................................. 38

4.9.3

TARGET TERMINATION RECEIVED BY PI7C7300D..................................................... 38

4.9.4

TARGET TERMINATION INITIATED BY PI7C7300D..................................................... 41

4.10

CONCURRENT MODE OPERATION..................................................................................... 42

ADDRESS DECODING .................................................................................................................. 42

PI7C7300D Datasheet(PDF) 5 Page - Pericom Semiconductor Corporation

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