PI7C7300D datasheet(6/107 Pages) PERICOM

6 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 6 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

5.1

ADDRESS RANGES................................................................................................................. 43

5.2

I/O ADDRESS DECODING...................................................................................................... 43

5.2.1

I/O BASE AND LIMIT ADDRESS REGISTER................................................................... 44

5.2.2

ISA MODE.......................................................................................................................... 45

5.3

MEMORY ADDRESS DECODING ......................................................................................... 45

5.3.1

MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS .............................. 46

5.3.2

PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ....................... 47

5.4

VGA SUPPORT......................................................................................................................... 48

5.4.1

VGA MODE........................................................................................................................ 48

5.4.2

VGA SNOOP MODE .......................................................................................................... 48

TRANSACTION ORDERING........................................................................................................ 49

6.1

TRANSACTIONS GOVERNED BY ORDERING RULES ..................................................... 49

6.2

GENERAL ORDERING GUIDELINES ................................................................................... 50

6.3

ORDERING RULES.................................................................................................................. 50

6.4

DATA SYNCHRONIZATION.................................................................................................. 52

ERROR HANDLING....................................................................................................................... 52

7.1

ADDRESS PARITY ERRORS .................................................................................................. 52

7.2

DATA PARITY ERRORS ......................................................................................................... 53

7.2.1

CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE ............... 53

7.2.2

READ TRANSACTIONS ..................................................................................................... 53

7.2.3

DELAYED WRITE TRANSACTIONS ................................................................................. 54

7.2.4

POSTED WRITE TRANSACTIONS.................................................................................... 56

7.3

DATA PARITY ERROR REPORTING SUMMARY .............................................................. 58

7.4

SYSTEM ERROR (SERR#) REPORTING ............................................................................... 63

EXCLUSIVE ACCESS .................................................................................................................... 63

8.1

CONCURRENT LOCKS ........................................................................................................... 64

8.2

ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300D .................................................. 64

8.2.1

LOCKED TRANSACTIONS IN DOWSTREAM DIRECTION............................................ 64

8.2.2

LOCKED TRANSACTION IN UPSTREAM DIRECTION.................................................. 65

8.3

ENDING EXCLUSIVE ACCESS ............................................................................................. 65

PCI BUS ARBITRATION............................................................................................................... 66

9.1

PRIMARY PCI BUS ARBITRATION ...................................................................................... 67

9.2

SECONDARY PCI BUS ARBITRATION................................................................................ 67

9.2.1

SECONDARY BUSARBITRATION USING THE INTERNAL ARBITER ........................... 67

9.2.2

PREEMPTION ................................................................................................................... 69

9.2.3

SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER............................ 69

9.2.4

BUS PARKING ................................................................................................................... 69

COMPACT PCI HOT SWAP ..................................................................................................... 70

CLOCKS ....................................................................................................................................... 70

11.1

PRIMARY CLOCK INPUTS .................................................................................................... 70

11.2

SECONDARY CLOCK OUTPUTS .......................................................................................... 70

RESET........................................................................................................................................... 71

12.1

PRIMARY INTERFACE RESET.............................................................................................. 71

12.2

SECONDARY INTERFACE RESET........................................................................................ 71

PI7C7300D Datasheet(PDF) 6 Page - Pericom Semiconductor Corporation

PI7C7300D Datasheet(HTML) 6 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL