PI7C7300DNA datasheet(33/107 Pages) PERICOM

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PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 33 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

PI7C7300D can recognize fast back-to-back read transactions.

4.8

CONFIGURATION TRANSACTIONS

Configuration transactions are used to initialize a PCI system. Every PCI device

has a configuration space that is accessed by configuration commands. All registers are

accessible in configuration space only.

In addition to accepting configuration transactions for initialization of its own

configuration space, the PI7C7300D also forwards configuration transactions for device

initialization in hierarchical PCI systems, as well as for special cycle generation.

To support hierarchical PCI bus systems, two types of configuration transactions are

specified: Type 0 and Type 1.

Type 0 configuration transactions are issued when the intended target resides on the same

PCI bus as the initiator. A Type 0 configuration transaction is identified by the

configuration command and the lowest two bits of the address set to 00b.

Type 1 configuration transactions are issued when the intended target resides on another

PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1

configuration command is identified by the configuration command and the lowest two

address bits set to 01b.

The register number is found in both Type 0 and Type 1 formats and gives the DWORD

address of the configuration register to be accessed. The function number is also included

in both Type 0 and Type 1 formats and indicates which function of a multifunction

device is to be accessed. For single-function devices, this value is not decoded. The

addresses of Type 1 configuration transaction include a 5-bit field designating the device

number that identifies the device on the target PCI bus that is to be accessed. In addition,

the bus number in Type 1 transactions specifies the PCI bus to which the transaction is

targeted.

4.8.1

TYPE 0 ACCESS TO PI7C7300D

The configuration space is accessed by a Type 0 configuration transaction on the primary

interface. The configuration space cannot be accessed from the secondary bus. The

PI7C7300D responds to a Type 0 configuration transaction by asserting P_DEVSEL#

when the following conditions are met during the address phase:

The bus command is a configuration read or configuration write transaction.

Lowest two address bits P_AD[1:0] must be 00b.

Signal P_IDSEL must be asserted.

Function code is either 0 for configuration space of S1, or 1 for configuration space of S2

as PI7C7300D is a multi-function device.

PI7C7300D limits all configuration access to a single DWORD data transfer and returns

target-disconnect with the first data transfer if additional data phases are requested.

PI7C7300DNA Datasheet(PDF) 33 Page - Pericom Semiconductor Corporation

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