PI7C7300DNA datasheet(84/107 Pages) PERICOM

84 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 84 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

Bit

Function

Type

Description

ISA enable

R/W

Modifies the bridge’s response to ISA I/O addresses, applying only to

those addresses falling within the I/O base and limit address registers

and within the first 64KB or PCI I/O space.

0: forward all I/O addresses in the range defined by the I/O base and

I/O limit registers

1: blocks forwarding of ISA I/O addresses in the range defined by the

I/O base and I/O limit registers that are in the first 64KB of I/O space

that address the last 768 bytes in each 1KB block. Secondary I/O

transactions are forwarded upstream if the address falls within the last

768 bytes in each 1KB block

Reset to 0

VGA enable

R/W

Controls the bridge’s response to VGA compatible addresses.

0: does not forward VGA compatible memory and I/O addresses from

primary to secondary

1: forward VGA compatible memory and I/O addresses from primary

to secondary regardless of other settings

Reset to 0

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

Master Abort

Mode

R/W

Control’s bridge’s behavior responding to master aborts on secondary

interface.

0: does not report master aborts (returns FFFF_FFFFh on reads and

discards data on writes)

1: reports master aborts by signaling target abort if possible by the

assertion of P_SERR# if enabled

Reset to 0

Secondary

Interface Reset

R/W

Controls the assertion of S1_RESET# or S2_RESET# signal pin on

the secondary interface

0: does not force the assertion of S1_RESET# or S2_RESET# pin

1: forces the assertion of S1_RESET# or S2_RESET#

Reset to 0

Fast Back-to-

Back Enable

R/W

Controls bridge’s ability to generate fast back-to-back transactions to

different devices on the secondary interface.

0: does not allow fast back-to-back transactions

1: enables fast back-to-back transactions

Reset to 0

Reserved

R/W

Reserved. Reset to 0

Reserved

R/W

Reserved. Reset to 0

Master Timeout

Status

R/WC

This bit is set to 1 when either the primary master timeout counter or

secondary master timeout counter expires.

Reset to 0

Discard Timer

P_SERR# enable

R/WC

This bit Is set to 1 and P_SERR# is asserted when either the primary

discard timer or the secondary S1 or S2 discard timer expire.

Reset to 0

31-28

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0.

PI7C7300DNA Datasheet(PDF) 84 Page - Pericom Semiconductor Corporation

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