PI7C7300DNA datasheet(8/107 Pages) PERICOM

8 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 8 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

14.1.42

SECONDARY SUCCESSFUL I/O WRITE COUNTER REGISTER – OFFSET 84h...... 91

14.1.43

SECONDARY SUCCESSFUL MEMORY READ COUNTER REGISTER – Offset 88h 92

14.1.44

SECONDARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER – OFFSET 8Ch

........................................................................................................................................ 92

14.1.45

PRIMARY SUCCESSFUL I/O READ COUNTER REGISTER – OFFSET 90h ............. 92

14.1.46

PRIMARY SUCCESSFUL I/O WRITE COUNTER REGISTER – OFFSET 94h............ 92

14.1.47

PRIMARY SUCCESSFUL MEMORY READ COUNTER REGISTER – OFFSET 98h .. 92

14.1.48

PRIMARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER – OFFSET 9Ch 93

14.1.49

CAPABILITY ID REGISTER – OFFSET B0h ................................................................ 93

14.1.50

NEXT POINTER REGISTER – OFFSET B0h ................................................................ 93

14.1.51

SLOT NUMBER REGISTER – OFFSET B0h................................................................. 93

14.1.52

CHASSIS NUMBER REGISTER – OFFSET B0h........................................................... 93

14.1.53

CAPABILITY ID REGISTER – OFFSET C0h ................................................................ 94

14.1.54

NEXT POINTER REGISTER – OFFSET C0h................................................................ 94

14.1.55

HOT SWAP CONTROL AND STATUS REGISTER – OFFSET C0h ............................. 94

BRIDGE BEHAVIOR.................................................................................................................. 94

15.1

BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES ............................................................ 95

15.2

TRANSACTION ORDERING .................................................................................................. 95

15.3

ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) ................................. 96

15.3.1

MASTER ABORT................................................................................................................ 96

15.3.2

PARITY AND ERROR REPORTING.................................................................................. 96

15.3.3

REPORTING PARITY ERRORS......................................................................................... 96

15.3.4

SECONDARY IDSEL MAPPING ....................................................................................... 97

IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................. 97

16.1

BOUNDARY SCAN ARCHITECTURE .................................................................................. 97

16.1.1

TAP PINS............................................................................................................................ 98

16.1.2

INSTRUCTION REGISTER................................................................................................ 98

16.2

BOUNDARY-SCAN INSTRUCTION SET.............................................................................. 99

16.3

TAP TEST DATA REGISTERS................................................................................................ 99

16.4

BYPASS REGISTER............................................................................................................... 100

16.5

BOUNDARY-SCAN REGISTER ........................................................................................... 100

16.6

TAP CONTROLLER ............................................................................................................... 100

ELECTRICAL AND TIMING SPECIFICATIONS............................................................... 103

17.1

MAXIMUM RATINGS ........................................................................................................... 103

17.2

3.3V DC SPECIFICATIONS ................................................................................................... 104

17.3

3.3V AC SPECIFICATIONS ................................................................................................... 105

17.4

PRIMARY AND SECONDARY BUSES AT 66MHZ CLOCK TIMING .............................. 106

17.5

PRIMARY AND SECONDARY BUSES AT 33MHZ CLOCK TIMING .............................. 106

17.6

POWER CONSUMPTION ...................................................................................................... 106

272-PIN PBGA PACKAGE FIGURE ...................................................................................... 107

18.1

PART NUMBER ORDERING INFORMATION ................................................................... 107

PI7C7300DNA Datasheet(PDF) 8 Page - Pericom Semiconductor Corporation

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