PI7C7300DNA datasheet(63/107 Pages) PERICOM

63 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 63 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

7.4

SYSTEM ERROR (SERR#) REPORTING

PI7C7300D uses the P_SERR# signal to report conditionally a number of system error

conditions in addition to the special case parity error conditions described in Section

7.2.3.

Whenever assertion of P_SERR# is discussed in this document, it is assumed that the

following conditions apply:

For PI7C7300D to assert P_SERR# for any reason, the SERR# enable bit must be

set in the command register.

Whenever PI7C7300D asserts P_SERR#, PI7C7300D must also set the signaled

system error bit in the status register.

In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7300D

asserts P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and

the SERR# forward enable bit is set in the bridge control register. In addition,

PI7C7300D also sets the received system error bit in the secondary status register.

PI7C7300D also conditionally asserts P_SERR# for any of the following reasons:

Target abort detected during posted write transaction

Master abort detected during posted write transaction

Posted write data discarded after 2

24 (default) attempts to deliver (224 target retries

received)

Parity error reported on target bus during posted write transaction (see previous

section)

Delayed write data discarded after 2

24 (default) attempts to deliver (224 target retries

received)

Delayed read data cannot be transferred from target after 2

24 (default) attempts (224

target retries received)

Master timeout on delayed transaction

The device-specific P_SERR# status register reports the reason for the assertion of

P_SERR#. Most of these events have additional device-specific disable bits in the

P_SERR# event disable register that make it possible to mask out P_SERR# assertion for

specific events. The master timeout condition has a SERR# enable bit for that event in

the bridge control register and therefore does not have a device-specific disable bit.

EXCLUSIVE ACCESS

This chapter describes the use of the LOCK# signal to implement exclusive access to a

target for transactions that cross PI7C7300D.

PI7C7300DNA Datasheet(PDF) 63 Page - Pericom Semiconductor Corporation

PI7C7300DNA Datasheet(HTML) 63 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL