PI7C7300DNA datasheet(38/107 Pages) PERICOM

38 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 38 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

For a posted write transaction, all write data for the transaction is transferred from

data buffers to the target.

For burst transfer, with the exception of “Memory Write and Invalidate”

transactions, the master latency timer expires and the PI7C7300D’s bus grant is de-

asserted.

The target terminates the transaction with a retry, disconnect, or target abort.

If PI7C7300D is delivering posted write data when it terminates the transaction because

the master latency timer expires, it initiates another transaction to deliver the remaining

write data. The address of the transaction is updated to reflect the address of the current

DWORD to be delivered.

If PI7C7300D is pre-fetching read data when it terminates the transaction because the

master latency timer expires, it does not repeat the transaction to obtain more data.

4.9.2

MASTER ABORT RECEIVED BY PI7C7300D

If the initiator initiates a transaction on the target bus and does not detect DEVSEL#

returned by the target within five clock cycles of the assertion of FRAME#, PI7C7300D

terminates the transaction with a master abort. This sets the received-master-abort bit in

the status register corresponding to the target bus.

For delayed read and write transactions, PI7C7300D is able to reflect the master abort

condition back to the initiator. When PI7C7300D detects a master abort in response to a

delayed transaction, and when the initiator repeats the transaction, PI7C7300D does not

respond to the transaction with DEVSEL# which induces the master abort condition back

to the initiator. The transaction is then removed from the delayed transaction queue.

When a master abort is received in response to a posted write transaction, PI7C7300D

discards the posted write data and makes no more attempts to deliver the data.

PI7C7300D sets the received-master-abort bit in the status register when the master abort

is received on the primary bus, or it sets the received master abort bit in the secondary

status register when the master abort is received on the secondary interface. When master

abort is detected in posted write transaction with both master-abort-mode bit (bit 5 of

bridge control register) and the SERR# enable bit (bit 8 of command register for

secondary bus S1 or S2) are set, PI7C7300D asserts P_SERR# if the master-abort-on-

posted-write is not set. The master-abort-on-posted-write bit is bit 4 of the P_SERR#

event disable register (offset 64h).

Note: When PI7C7300D performs a Type 1 to special cycle conversion, a master abort is

the expected termination for the special cycle on the target bus. In this case, the master

abort received bit is not set, and the Type 1 configuration transaction is disconnected

after the first data phase.

4.9.3

TARGET TERMINATION RECEIVED BY PI7C7300D

When PI7C7300D initiates a transaction on the target bus and the target responds with

DEVSEL#, the target can end the transaction with one of the following types of

termination:

PI7C7300DNA Datasheet(PDF) 38 Page - Pericom Semiconductor Corporation

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