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MB9AF112K Datasheet(PDF) 5 Page - SPANSION |
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MB9AF112K Datasheet(HTML) 5 Page - SPANSION |
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5 / 89 page ![]() D a t a S h e e t 2 MB9A110K-DS706-00030-2v0-E, February 20, 2015 CONFIDENTIAL Features 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 40MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC) : 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick) : System timer for OS task management On-chip Memories [Flash memory] This Series are based on two independent on-chip Flash memories. MainFlash Up to 128Kbyte Read cycle : 0 wait-cycle Security function for code protection WorkFlash 32Kbyte Read cycle : 0 wait-cycle Security function is shared with code protection [SRAM] This Series contain a total of up to 16Kbyte on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1) . SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0 : 8 Kbyte SRAM1 : 8 Kbyte |
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