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ADSP-SC583 Datasheet(PDF) 32 Page - Analog Devices |
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ADSP-SC583 Datasheet(HTML) 32 Page - Analog Devices |
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32 / 168 page  Rev. PrF | Page 32 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data DMC0_DQ13 DMC0 Data 13 Not Muxed DMC0_DQ13 DMC0_DQ14 DMC0 Data 14 Not Muxed DMC0_DQ14 DMC0_DQ15 DMC0 Data 15 Not Muxed DMC0_DQ15 DMC0_LDM DMC0 Data Mask for Lower Byte Not Muxed DMC0_LDM DMC0_LDQS DMC0 Data Strobe for Lower Byte Not Muxed DMC0_LDQS DMC0_LDQS DMC0 Data Strobe for Lower Byte (complement) Not Muxed DMC0_LDQS DMC0_ODT DMC0 On-die termination Not Muxed DMC0_ODT DMC0_RAS DMC0 Row Address Strobe Not Muxed DMC0_RAS DMC0_RESET DMC0 Reset (DDR3 only) Not Muxed DMC0_RESET DMC0_RZQ DMC0 External calibration resistor connection Not Muxed DMC0_RZQ DMC0_UDM DMC0 Data Mask for Upper Byte Not Muxed DMC0_UDM DMC0_UDQS DMC0 Data Strobe for Upper Byte Not Muxed DMC0_UDQS DMC0_UDQS DMC0 Data Strobe for Upper Byte (complement) Not Muxed DMC0_UDQS DMC0_VREF DMC0 Voltage Reference Not Muxed DMC0_VREF DMC0_WE DMC0 Write Enable Not Muxed DMC0_WE ETH0_CRS ETH0 Carrier Sense/RMII Receive Data Valid A PA_07 ETH0_MDC ETH0 Management Channel Clock A PA_02 ETH0_MDIO ETH0 Management Channel Serial Data A PA_03 ETH0_PTPAUXIN0 ETH0 PTP Auxiliary Trigger Input 0 B PB_03 ETH0_PTPAUXIN1 ETH0 PTP Auxiliary Trigger Input 1 B PB_04 ETH0_PTPAUXIN2 ETH0 PTP Auxiliary Trigger Input 2 B PB_05 ETH0_PTPAUXIN3 ETH0 PTP Auxiliary Trigger Input 3 B PB_06 ETH0_PTPCLKIN0 ETH0 PTP Clock Input 0 B PB_02 ETH0_PTPPPS0 ETH0 PTP Pulse-Per-Second Output 0 B PB_01 ETH0_PTPPPS1 ETH0 PTP Pulse-Per-Second Output 1 B PB_00 ETH0_PTPPPS2 ETH0 PTP Pulse-Per-Second Output 2 A PA_15 ETH0_PTPPPS3 ETH0 PTP Pulse-Per-Second Output 3 A PA_14 ETH0_RXCLK_REFCLK ETH0 RXCLK (GigE) or REFCLK (10/100) A PA_06 ETH0_RXCTL_CRS ETH0 RXCTL (GigE) or CRS (10/100) A PA_07 ETH0_RXD0 ETH0 Receive Data 0 A PA_04 ETH0_RXD1 ETH0 Receive Data 1 A PA_05 ETH0_RXD2 ETH0 Receive Data 2 A PA_08 ETH0_RXD3 ETH0 Receive Data 3 A PA_09 ETH0_TXCLK ETH0 Transmit Clock A PA_11 ETH0_TXCTL_TXEN ETH0 TXCTL (GigE) or TXEN (10/100) A PA_10 ETH0_TXD0 ETH0 Transmit Data 0 A PA_00 ETH0_TXD1 ETH0 Transmit Data 1 A PA_01 ETH0_TXD2 ETH0 Transmit Data 2 A PA_12 ETH0_TXD3 ETH0 Transmit Data 3 A PA_13 ETH0_TXEN ETH0 Transmit Enable A PA_10 HADC0_VIN0 HADC0 Analog Input at channel 0 Not Muxed HADC0_VIN0 HADC0_VIN1 HADC0 Analog Input at channel 1 Not Muxed HADC0_VIN1 HADC0_VIN2 HADC0 Analog Input at channel 2 Not Muxed HADC0_VIN2 HADC0_VIN3 HADC0 Analog Input at channel 3 Not Muxed HADC0_VIN3 HADC0_VIN4 HADC0 Analog Input at channel 4 Not Muxed HADC0_VIN4 HADC0_VIN5 HADC0 Analog Input at channel 5 Not Muxed HADC0_VIN5 HADC0_VIN6 HADC0 Analog Input at channel 6 Not Muxed HADC0_VIN6 HADC0_VIN7 HADC0 Analog Input at channel 7 Not Muxed HADC0_VIN7 Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued) Signal Name Description Port Pin Name |
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