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ADSP-SC583 Datasheet(PDF) 33 Page - Analog Devices

Part # ADSP-SC583
Description  SHARC plus Dual Core DSP with ARM Cortex-A5
PDF  168 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-SC583 Datasheet(HTML) 33 Page - Analog Devices

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Preliminary Technical Data
Rev. PrF
|
Page 33 of 168
|
February 2016
ADSP-SC582/583/584/587/589/ADSP-21583/584/587
HADC0_VREFN
HADC0 Ground Reference for ADC
Not Muxed
HADC0_VREFN
HADC0_VREFP
HADC0 External Reference for ADC
Not Muxed
HADC0_VREFP
JTG_TCK
TAPC JTAG Clock
Not Muxed
JTG_TCK
JTG_TDI
TAPC JTAG Serial Data In
Not Muxed
JTG_TDI
JTG_TDO
TAPC JTAG Serial Data Out
Not Muxed
JTG_TDO
JTG_TMS
TAPC JTAG Mode Select
Not Muxed
JTG_TMS
JTG_TRST
TAPC JTAG Reset
Not Muxed
JTG_TRST
LP0_ACK
LP0 Acknowledge
D
PD_11
LP0_CLK
LP0 Clock
D
PD_10
LP0_D0
LP0 Data 0
D
PD_02
LP0_D1
LP0 Data 1
D
PD_03
LP0_D2
LP0 Data 2
D
PD_04
LP0_D3
LP0 Data 3
D
PD_05
LP0_D4
LP0 Data 4
D
PD_06
LP0_D5
LP0 Data 5
D
PD_07
LP0_D6
LP0 Data 6
D
PD_08
LP0_D7
LP0 Data 7
D
PD_09
LP1_ACK
LP1 Acknowledge
B
PB_15
LP1_CLK
LP1 Clock
C
PC_00
LP1_D0
LP1 Data 0
B
PB_07
LP1_D1
LP1 Data 1
B
PB_08
LP1_D2
LP1 Data 2
B
PB_09
LP1_D3
LP1 Data 3
B
PB_10
LP1_D4
LP1 Data 4
B
PB_11
LP1_D5
LP1 Data 5
B
PB_12
LP1_D6
LP1 Data 6
B
PB_13
LP1_D7
LP1 Data 7
B
PB_14
MLB0_CLKN
MLB0 Differential Clock (–)
Not Muxed
MLB0_CLKN
MLB0_CLKP
MLB0 Differential Clock (+)
Not Muxed
MLB0_CLKP
MLB0_DATN
MLB0 Differential Data (–)
Not Muxed
MLB0_DATN
MLB0_DATP
MLB0 Differential Data (+)
Not Muxed
MLB0_DATP
MLB0_SIGN
MLB0 Differential Signal (–)
Not Muxed
MLB0_SIGN
MLB0_SIGP
MLB0 Differential Signal (+)
Not Muxed
MLB0_SIGP
MLB0_CLK
MLB0 Single-Ended Clock
B
PB_04
MLB0_DAT
MLB0 Single-Ended Data
B
PB_06
MLB0_SIG
MLB0 Single-Ended Signal
B
PB_05
MLB0_CLKOUT
MLB0 Single-Ended Clock Out
D
PD_14
PA_00-15
PORTA Position 00 through Position 15
A
PA_00-15
PB_00-15
PORTB Position 00 through Position 15
B
PB_00-15
PC_00-15
PORTC Position 00 through Position 15
C
PC_00-15
PD_00-15
PORTD Position 00 through Position 15
D
PD_00-15
PE_00-15
PORTE Position 00 through Position 15
E
PE_00-15
PPI0_CLK
EPPI0 Clock
E
PE_03
PPI0_D00
EPPI0 Data 0
E
PE_12
PPI0_D01
EPPI0 Data 1
E
PE_11
PPI0_D02
EPPI0 Data 2
E
PE_10
PPI0_D03
EPPI0 Data 3
E
PE_09
PPI0_D04
EPPI0 Data 4
E
PE_08
Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
Description
Port
Pin Name



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