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ADSP-SC583 Datasheet(PDF) 86 Page - Analog Devices |
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ADSP-SC583 Datasheet(HTML) 86 Page - Analog Devices |
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86 / 168 page ![]() Rev. PrF | Page 86 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data The following equation is used to compute the power dissipa- tion when the FFT accelerator is used: IDDINT_ACCL_DYN (mA) = ASFACCL × fSYSCLK (MHz) × VDD_INT (V) Clock Current The dynamic clock currents provide the total power dissipated by all transistors switching in the clock paths. The power dissi- pated by each clock domain is dependent on voltage (VDD_INT), operating frequency and a unique scaling factor. IDDINT_SYSCLK_DYN (mA) = 0.80 × fSYSCLK (MHz) × VDD_INT (V) IDDINT_SCLK0_DYN (mA) = 0.40 × fSCLK0 (MHz) × VDD_INT (V) IDDINT_SCLK1_DYN (mA) = 0.04 × fSCLK1 (MHz) × VDD_INT (V) IDDINT_DCLK_DYN (mA) = 0.14 × fDCLK (MHz) × VDD_INT (V) IDDINT_OCLK_DYN (mA) = 0.005 × fOCLK (MHz) × VDD_INT (V) Current from High Speed Peripheral Operation The following modules contribute significantly to power dissi- pation and a single term is added when they are used. IDDINT_USB_DYN = 20 mA (if USB enabled) IDDINT_MLB_DYN = 10 mA (if MLB 6-pin interface is enabled) IDDINT_GIGE_DYN = 10 mA (if Gigabit Ethernet MAC controller is enabled) Data Transmission Current The data transmission current represents the power dissipated when transmitting data. This current is proportional to the data rate. Refer to the power calculator of this product to estimate IDDINT_DMA_DR_DYN based on the bandwidth of the data transfer. Table 34. CCLK Dynamic Current per ARM Cortex-A5 Core (mA, with ASF = 1.00) fCCLK (MHz) Voltage (VDD_INT) 1.000 1.050 1.100 1.150 1.200 450 49.5 52.0 54.5 56.9 59.4 400 44.0 46.2 48.4 50.6 52.8 350 38.5 40.4 42.4 44.3 46.2 300 33.0 34.7 36.3 38.0 39.6 250 27.5 28.9 30.3 31.6 33.0 200 22.0 23.1 24.2 25.3 26.4 150 16.5 17.3 18.2 19.0 19.8 100 11.0 11.6 12.1 12.7 13.2 Table 35. Activity Scaling Factors for FFT Accelerator (ASFA5) IDDINT Power Vector ASFACCL Unused 0.0 IDD-TYPP 0.4 |
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