TMP320C2811PBKA datasheet(130/147 Pages) TI

130 / 147 page

Electrical Specifications

130

June 2004

SPRS257

ADCIN0

10 pF

Ron

1 kΩ

1.25 pF

Switch

Typical Values of the Input Circuit Components:

Switch Resistance (Ron):

1 kΩ

Sampling Capacitor (Ch):

1.25 pF

Parasitic Capacitance (Cp): 10 pF

Source Resistance (Rs):

50 Ω

28x DSP

Source

Signal

Figure 6−34. ADC Analog Input Impedance Model

6.29.4 ADC Power-Up Control Bit Timing

ADC Power Up Delay

ADC Ready for Conversions

PWDNBG

PWDNREF

PWDNADC

Request for

ADC

Conversion

td(BGR)

td(PWD)

Figure 6−35. ADC Power-Up Control Bit Timing

Table 6−40. ADC Power-Up Delays†

MIN

TYP

MAX

UNIT

td(BGR)

Delay time for band gap reference to be stable. Bits 6 and 5 of the ADCTRL3 register

(PWDNBG and PWDNREF) are to be set to 1 before the PWDNADC bit is enabled.

Delay time for power-down control to be stable. Bit 7 of the ADCTRL3 register

µs

td(PWD)

Delay time for power down control to be stable. Bit 7 of the ADCTRL3 register

(PWDNADC) is to be set to 1 before any ADC conversions are initiated.

† These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If conversions

are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at the same time.

TMP320C2811PBKA Datasheet(PDF) 130 Page - Texas Instruments

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