8 11

AGND

ADC08B200

D7

D6

D5

D0

D1

D2

D3

D4

6

3

+3.3V

110

5

30

DR GND

10

10 PF

+

301

2

46

CLK

0.1 PF

9

0.1 PF

10 PF

+

1

4

32

0.1 PF

10 PF

Choke

0.1 PF

10 PF

+

12

+3.3V

1

%

1

%

0.1 PF

1.9V

nomina

l

7

38

MUL0

39

MUL1

BSIZE0

BSIZE1

24

23

DRDY

31

OE

40

OEDGE

14

EF

15

FF

16

REN

20

WEN

17

21 42 45 47

43 44 48

+

10 PF

0.1 PF

RCLK

19

ASW

25

18

WENsync

37

RESET

22

PD

13

26

27

28

36

35

34

33

29

PDADC

41

ADC08B200

SNAS388F – MARCH 2007 – REVISED APRIL 2013

www.ti.com

The RESET signal resets the read and write pointers and the EF and FF flags. The RESET signal also stops the

read operation early (before the EF flag goes high). Consequently, only a partial read is performed if the RESET

input goes high while a buffer read out is under way. This allows the buffer pointers to be reset so a new capture

operation can begin. The RESET signal has no effect upon the A/D converter, which has its own internal Power-

On Reset circuit.

Note that the RCLK input does not need to be as noise (jitter) free as does the CLK signal. The reason for this is

that RCLK is only used to read the Capture Buffer, while the CLK signal is either the ADC sample clock or is the

reference for the internal PLL that generates the sample clock for the ADC. Consequently, CLK jitter directly

affects the ADC's SNR performance. There is no requirement for the RCLK to have any fixed relationship with

CLK in terms of phase or frequency.

Applications Information

REFERENCE INPUTS

between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should

be within the range specified in OPERATING RATINGS and ELECTRICAL CHARACTERISTICS. Any device

Because of the ladder and external resistor tolerances, the reference voltage of this circuit can vary too much for

some applications.

Figure 44. Simple, Low Component Count Reference Biasing

The reference bias circuit of Figure 44 is very simple and the performance is adequate for many applications.

However, circuit tolerances will lead to a wide reference voltage range. Better reference tolerance can be

achieved by driving the reference pins with low impedance sources.

The circuit of Figure 45 will allow a more accurate setting of the reference voltages, with upper and lower

reference accuracies of about 16 mV, or about 2 1/2 LSB. The upper amplifier must be able to source the

amplifier must be able to sink this reference current. Both amplifiers should be stable with a capacitive load.

22

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