4.7k

0.1 µF

309W

470W

1/2

LM8272

-

+

1

8

4

3

2

10 mF

+

+3.3V

0.01 µF

1 µF

1/2

LM8272

+

-

6

5

1.62k

0.01 µF

7

604W

LM4040-2.5

0.1 µF

0.1 µF

1 µF

4.7k

1 µF

8 11

GND

ADC08B200

D7

D6

D5

D0

D1

D2

D3

D4

3

5

30

DR GND

10

V

RT

2

CLK

9

0.1 µF

10 µF

+

1

4

32

0.1 µF

10 µF

V

DR

V

A

Choke

0.1 µF

10 µF

+

12

7

V

GND

IN

38

MULT0

39

MULT1

BSIZE0

BSIZE1

24

23

DRDY

31

OE

40

OEDGE

14

EF 15

FF

16

REN 20

WEN

17

21 42 45 47

43

44 48

+

10 µF

0.1 µF

V

P

RCLK

19

ASW 25

18

WENsync

37

RESET

22

V

D

PD 13

26

27

28

36

35

34

33

29

PDADC

41

V

RM

V

RB

+3.3V

+3.3V

+3.3V

CLK

OSC

(50MHz)

+3.3V

0.1µF

33

Processor / PLD /

FPGA / DSP

33

6

V

IN

46

22

+

-

200

18

240

47

100

33 pF

Signal

Input

LMH6702

+5V

0.1 µF

33

33

33

33

33

33

33

33

33

33

33

33

33

33

+3.3V

ADC08B200

SNAS388F – MARCH 2007 – REVISED APRIL 2013

www.ti.com

The OEDGE pin is high, meaning the output data will transition at the rise of the DRDY output. Since the PD pin

is grounded and the OE pin is high, the device will never be completely powered down and the outputs are

always enabled. Since the PDADC pin is driven from the controlling device, the ADC may be powered down,

leaving the output buffer active, when the device buffer is being read, or when the device is not in use.

The digital lines between the ADC08B200 and the receiving device have 33 Ohms at the signal source end as

source terminators, assuming output impedances of about 20 Ohms and 50-Ohm lines. The RESET and PDADC

lines are not terminated because these are basically d.c. lines and it is assumed that they do not toggle

frequently.

Figure 47. Example of a Typical Application

The average power consumption of the ADC08B200 (assuming a new capture is taken as soon as the buffer

contents is read) may be calculated by taking power consumed while capturing and writing to the buffer and

multiplying it by the capture time divided by the throughput time (interval between the successive rises of the

WEN signal), added to the power while reading the buffer with PDADC high (assuming the PDADC input is taken

high whenever data is not being captured) multiplied by the time that PDADC is high (Buffer read time plus any

idle time) divided by the throughput rate.

Assuming a Capture Power of 543 mW, a 200 Msps capture rate and a 66mW Read Power with PDADC high, a

50 MHz data read rate and no completely idle time, the average power consumption would be 161.4 mW.

32

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