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ADC08B200CIVS/NOPB Datasheet(PDF) 10 Page - Texas Instruments |
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ADC08B200CIVS/NOPB Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 39 page ![]() ADC08B200 SNAS388F – MARCH 2007 – REVISED APRIL 2013 www.ti.com CONVERTER TIMING CHARACTERISTICS (continued) The following specifications apply for VA = VDR = +3.3VDC, VRT = +1.9V, VRB = 0.3V, CL = 50 pF, fCLK = 200 MHz at 50% duty cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1)(2) Units Parameter Test Conditions Typ (3) Limits (3) (Limits) CL = 10 pF 1.4 ns Output Data Fall Time tf (2.4V to 0.4V) CL = 20 pF 3.2 ns 4.0 ns (min) Reading Buffer 7.0 RCLK Rising Edge to Data Output 11.7 ns (max) tODF Fall to 0.4V Buffer bypassed, PLL disabled 5.5 ns 2.3 ns (min) Reading Buffer 6.5 RCLK Rising Edge to Data Output 13.1 ns (max) tODR Rise to 2.5V Buffer bypassed, PLL disabled 5.5 ns RCLK Rising Edge to Data Output 2.4 ns (min) tOHF Reading Buffer 3.8 Fall to 2.5V 5.5 ns (max) RCLK Rising Edge to Data Output 2.6 ns (min) tOHR Reading Buffer 4.5 Rise to 0.4V 6.9 ns (max) Output Falling (2.4V to 0.4V) 1.5 V / ns tSLEW Output Slew Rate Output Rising (0.4V to 2.5V) 2.3 V / ns PLL Enabled 20 µs tDRDY1 PD Low to Device Active PLL Bypassed 2 µs tDRDY2 PDADC Low to Device Active 2 µs Pipeline Delay (Latency) 6 Clock Cycles PLL on 3.4 ns CLK Rise to tAD Sampling (Aperture) Delay Acquisition of Data PLL off 3.9 ns PLL Bypassed 2 ps rms tAJ Aperture Jitter PLL Enabled in x8 mode (6) 7 ps rms (6) Jitter with the PLL enabled is measured with 32k samples and the PLL in the x8 multiplication mode. SPECIFICATION DEFINITIONS APERTURE (SAMPLING) DELAY is that time delay after the rise of the sample clock until the input signal is sampled within the ADC. APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise. CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one clock period. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. Measured at 200 MSPS with a ramp input. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below VRT and is defined as: FSE = Vmax + 1.5 LSB – VRT where • Vmax is the voltage at which the transition to the maximum (full scale) code occurs (1) INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: ADC08B200 |
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