ADC08B200

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SNAS388F – MARCH 2007 – REVISED APRIL 2013

possible to, but within one centimeter of, the ADC08B200 clock pin. Furthermore, this termination should be

beyond the receiving pin as seen from the clock source. For FR-4 board material, the value of C becomes

where

•

L is the length of the clock line in inches

(7)

The RESET Pin

A high level at this Reset input resets all control logic on the chip, including the buffer's read and write counters.

The FF output is reset low and the EF flag is reset high upon a device reset. Invoking a reset during the WRITE

phase can cause buffer data to be corrupted. A reset during the READ phase will stop the READ phase before it

is completed.

The RESET signal is asynchronous and should be at least 4 sample clock cycles wide. If no RESET is provided,

the chip generates its own internal reset signal at the beginning of the buffer write phase.

The OEDGE/TEN Pin

If this Output Edge Select input is high, the data outputs transition with the rising edge of the DRDY output. If this

enables the Test Mode. There is an on-chip pull-up resistor at this pin, so the device interprets a floating input at

this pin to be a logic high. See TEST PATTERN OUTPUT for the output test pattern.

The OE Pin

A high level at this Output Enable input enables the output buffers. A low level at this input puts the digital data

output pins, including the DRDY output, into a high impedance state. The only exception is in the Test Pattern

Mode, where the OE input is ignored and the DRDY and data output pins are active regardless of the OE pin

status.

CAUTION

Although this device has a TRI-STATE output, maintaining optimum noise performance

requires keeping the capacitance on the data output pins as low as possible.

Therefore, it is never a good idea to connect the output pins to a bus. Each output pin

should be connected to a single input with lines as short as possible.

Buffer-Associated Pins

The on-chip buffer is 1 kilobyte (1,024 bytes) in size and is controlled through six (6) TTL-CMOS compatible

digital input pins.

THE RCLK PIN

When the capture buffer is enabled, the RCLK input is used to read the data from the buffer. The data output and

the EF flag transition with the rise of RCLK.

It is best to halt the RCLK when not reading the buffer to minimize its impact upon noise performance. RCLK

may be stopped in either the high or the low state.

THE WEN PIN

A high level at this Write Enable input causes data to be written into the capture buffer. One byte is written with

the rise of each sample clock. This input may go high asynchronously.

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