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TMS320C6472ECTZ Datasheet(PDF) 230 Page - Texas Instruments |
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TMS320C6472ECTZ Datasheet(HTML) 230 Page - Texas Instruments |
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230 / 269 page  RMREFCLK (input) 1 3 4 4 2 TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.15.4.2 EMAC RMII Electrical Data/Timing The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation. The RMREFCLK frequency should be 50 MHz ±50 PPM with a duty cycle between 35% and 65%, inclusive. Table 7-116. Timing Requirements for RMREFCLK - RMII Operation (see Figure 7-52) 500/625/700 NO. PARAMETER UNIT MIN TYP MAX 1 tc(RFCK) Cycle time, REFCLK 20 ns 2 tw(RFCKH) Pulse duration, REFCLK high 7 13 ns 3 tw(RFCKL) Pulse duration, REFCLK low 7 13 ns 4 tt(RFCK) Transition time, REFCLK 2 ns Figure 7-52. RMII Reference Clock (Input) Table 7-117. Timing Requirements for EMAC RMII Receive 500/625/700 UNIT PARAMETER MIN MAX tsu(RXD-RFCK) Setup time, RXD to REFCLK rising edge 4 ns tsu(CDV-RFCK) Setup time, CRSDV to REFCLK rising edge 4 ns tsu(RXER-RFCK) Setup time, RXER to REFCLK rising edge 4 ns th(RFCK-RXD) Hold time, RXD valid after REFCLK rising edge 2 ns th(RFCK-CDV) Hold time, CRSDV valid after REFCLK rising edge 2 ns th(RFCK-RXER) Hold time, RXER valid after REFCLK rising edge 2 ns Table 7-118. Timing Requirements for EMAC RMII Transmit 500/625/700 UNIT PARAMETER MIN MAX td(RFCK-TXDV) Delay time, REFCLK rising edge to TXD 2.5 13 ns td(RFCK-TXENV) Delay time, REFCLK rising edge to TXENV 2.5 13 ns 230 C64x+ Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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