ML7396AB datasheet(64/140 Pages) LAPIS

64 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

64/140

Interrupt notification

Reference point

Time from reference point to interrupt generation

or interrupt generation timing

INT[8]

CCA completion

CCA execution start

(1)Normal mode

{ED value calculation averaging time + IDLE_WAIT setting

[IDLE_WAIT_L/H:B0 0x17/18] + 2 (filter stbilization)} * A/D

conversion time

(2) IDLE detection mode

IDLE detection case

{ED value calculation averaging time + IDLE_WAIT setting

[IDLE_WAIT_L/H:B0 0x17/18] + 2(filter stbilization)} * A/D

conversion time

BUSY detection case

(ED value calculation averaging tim+ 2(filter stbilization)) * A/D

conversion

Note: A/D conversion time can be changed by ADC_CLK_SET

(ADC_CLK_SET:B0 0x08(4)). ADC conversion time= 17.7μs

(1.8MHz), 16μs (2.0MHz)

Note: When executing CCA during diversity, set the abort timer

for CCA completion notification. When CCA is run during

diversity, since there is a case CCA completion is not notified.

INT[9]

Diversity search

completion

diversity search completion

TX_ON command

(IDLE) 122μs

(RX) 89μs

RX_ON command

(IDLE) 136μs

(TX) 142μs

TRX_OFF

command

(TX) 410μs

(RX) 11μs

INT[10]

RF state transition

completion

Force_TRX_OFF

command

(TX) 410μs

(RX) 10μs

INT[11]

SFD detection

INT[12]

RX length error

SFD detection

80μs

INT[13]

TX length error

Writing TX data to a FIFO

INT[14]

RX FIFO access error

(1).receiving 3

rd packet with remaining RX dara in both FIFO0

and FIFO1

(2) overfolow occurs because FIFO read is too slow

(3) underflow occurs because too many FIFO data is read

INT[15]

TX FIFO access error

(1) writing 3

rd packet with remaining TX data in both FIFO0 and

FIFO1

(2) FIFO overflow when writing

(3) FIFO underflow (or no data) when transmitting

INT[16]

INT[17]

FIFO0/FIFO1 TX

completion

TX_ON command

(* 1)

(When FEC is disabled)

40byte (preamble to CRC) * 8bit * 10(symbol time) +

RF wake-up & process delay(154μs) =3354μs

(When FEC is enabled)

{12byte (preamble to SFD) + 28byte (Length to CRC) * 2} * 8bit

* 10(symbol time) + RF wake-up & process delay(224μs)

=5664μs

(* 1) Befor issuing TX_ON, writing full-length TX data into a FIFO.

ML7396AB Datasheet(PDF) 64 Page - LAPIS Semiconductor Co., Ltd.

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