ML7396AB datasheet(92/140 Pages) LAPIS

92 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

92/140

[Flowchart]

START

* RX_FIFO_MON ([PLL_MON/DIO_SEL:B0 0x69(0)])

setting does not affect on DIO (TX) mode operation.

TX_ON issue

[RF_STATUS:B0 0x6C]

END

Yes

Input TX data

[DIO pin (#15)]

Write dummy data to a FIFO

Yes

Next packet TX?

Yes

TX data request accept completion int?

[INT_SOURCE_GRP3:B0 0x26]

Clear TX data request accept

completion interrupt

[INT_SOURCE_GRP3:B0 0x26]

Packet header setting

[PREAMBLE_SET:B0 0x39]

[SFD1_SET1-4:B0 0x3A-3D]

[TX_PR_LEN:B0 0x42]

[RX_PR_LEN/SFD_LEN:B0 0x43]

Set DIO_EN =0b1

[PLL_MON/DIO_SEL:B0 0x69(2)]

Set “L/H” to DIO pin

* Set 1st biy of TX data to the DIO pin.

* Set CRC_DONE ([FEX/CRC_SET:B0 0x46(0)])=0b0

(disable) and write 0x00-01-02 to [WR_TX_FIFO:B0

0x7E] register.

* If issuing TX_ON before writing dummy

data, same result can be achieved

* Timing up to DCLK output varies

depending on preamble length, SFD

length and data rate

DCLK output?

[DCLK pin (#16)]

* TX data should be input at falling edge of DCLK.

TX completion?

TRX_OFF issue

[RF_STATUS:B0 0x6C]

ML7396AB Datasheet(PDF) 92 Page - LAPIS Semiconductor Co., Ltd.

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