ML7396AB datasheet(91/140 Pages) LAPIS

91 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

91/140

TX data corresponding to each register setting and DIO input is as below:

[Example] Transmitting prEN 13757-4rev Mode C format A packet (ML7396E)

Case 1: Input TX data at rising edge of DCLK

[Conditions]

[PREAMBLE_SET:B0 0x39] =0x55

[SFD1_SET1:B0 0x3A] =0x55

[SFD1_SET2:B0 0x3B] =0x55

[TX_PB_LEN:B0 0x42] =0x03

[RX_PR_LEN/SFD_LEN:B0 0x43] =0x02

Case 2: Input TX data at falling edge of DCLK

[Conditions]

[PREAMBLE_SET:B0 0x39]=0xAA

[SFD1_SET1:B0 0x3A] =0xAA

[SFD1_SET2:B0 0x3B] =0xAA

[TX_PB_LEN:B0 0x42] =0x03

[RX_PR_LEN/SFD_LEN:B0 0x42] =0x02

PREAMBLE

SyncWord

Data

DIO input

(SyncWord)

DCLK output

DIO input

(Data)

TX data (Air)

PREAMBLE_SET

(3Byte)

SFD1_SET1

(1Byte)

SFD1_SET2

(1Byte)

0101010101 01010101 01010101 01010101 0101 0100 0011 1101 0101 0100 1100 1101 xxxx ….

Pre-set “L” to DIO pin.

These 2 bits will be transmitted

as 1st bit and 2nd bit.

Sending data following last

3 bytes of SyncWord.

PREAMBLE

SyncWord

PREAMBLE_SET

(3Byte)

SFD1_SET2

(1Byte)

Pre-set “L” to DIO pin.

This bit will be transmitted

as 1st bit

Sending data following last

3 bytes of SyncWord.

101010101 01010101 01010101 01010101 0101 0100 0011 1101 0101 0100 1100 1101 xxxx ….

SFD1_SET1

(1Byte)

Data

DCLK output

TX data (Air)

DIO input

(SyncWord)

DIO input

(Data)

ML7396AB Datasheet(PDF) 91 Page - LAPIS Semiconductor Co., Ltd.

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