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ML7396AB Datasheet(PDF) 61 Page - LAPIS Semiconductor Co., Ltd.

Part # ML7396AB
Description  Sub GHz band short range wireless transceiver IC
PDF  140 Pages
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Manufacturer  LAPIS [LAPIS Semiconductor Co., Ltd.]
Direct Link  http://www.lapis-semi.com/
Logo LAPIS - LAPIS Semiconductor Co., Ltd.

ML7396AB Datasheet(HTML) 61 Page - LAPIS Semiconductor Co., Ltd.

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FEDL7396A/B/E-07
ML7396A/B/E
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[Interrupts timing when using INT_TIM_CTRL]
By setting INT_TIM_CTRL ([PLL_MOD/DIO_SEL:B0 0x69(6)]), it is possible to select interrupt timing during Address
filtering mode.
According to the ADDFIL_NG_SET or ADDFIL_IDLE_DET setting and CRC result in the RX packet, interrupt generation
timings of
Packet discard completion interrupt,
CRC error interrupt, and
CCA completion interrupt, will become as
below figures.
Setting 1
Setting 2
Setting 3
Setting 4
Setting
setting register
Case1
Case2
Case3
Case4
Case5
Case6
Case7
Case8
Discard packet
after address
mismatch
ADDFIL_NG_SET=0b0
O
O
-
-
O
O
-
-
Discar packet after
address mismatch
and RX completion
ADDFIL_NG_SET=0b1
-
-
O
O
-
-
O
O
Execute CCA after
address mismatch
ADDFIL_IDLE_DET=0b 1
-
-
-
-
O
O
O
O
CRC_OK
-
O
-
O
-
O
-
O
-
CRC_NG
-
-
O
-
O
-
O
-
O
Packet discard
cpmpletion interrupt
INT[3]
[INT_SOURCE_GRP1]
O
O
O
O
O
O
O
O
CRC error interrupt
INT[21/20]
[INT_SOURCE_GRP3]
O
O
-
O
O
O
-
O
CCA completion
interrupt
INT[8]
[INT_SOURCE_GRP2]
-
-
-
-
O
O
O
O
(1) When INT_TIM_CTRL=0b0 (timing is comatible with ML7396)
Case1
to : 1111ns
Case2
to : 1111ns
Case3
Case4
and
at same time
Case5
to : 555ns
Case6
to : 555ns
Case7
to : 555ns
Case8
to : 555ns
(2) When INT_TIM_CTRL=0b1 (ML7396B timing)
Case1
: 1111ns
Case2
to : 1111ns
Case3
Case4
and
at same time
Case5
Case6
Case7
Case8
MAC
HDR
PHY
HDR
DATA
CCA
(IDLE detection)



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