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ML7396AB Datasheet(PDF) 75 Page - LAPIS Semiconductor Co., Ltd. |
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ML7396AB Datasheet(HTML) 75 Page - LAPIS Semiconductor Co., Ltd. |
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75 / 140 page  FEDL7396A/B/E-07 ML7396A/B/E 75/140 ●Programming BPF band width For normal operation (including AFC) and CCA operation, optimized BPF setting are necessary. To compensating LSI variations, [BPF_ADJ_OFFSET:B1 0x1E] register indicates individual cpmpensation value. According to the below table, multiplying BPF_OFFSET[6:0] ([BPF_ADJ_OFFSET:B1 0x1E(6-0)]) by the coefficient value corresponding to each data rate. If BPF_OFFSET_POL ([BPF_ADJ_OFFSET:B1 0x1E(7)] = 0b1, incraseing, otherwise (=0b0) decrasing to the default value corresponding each data rate. Compensated value is set into [BPF_ADJ_H/L:B1 0x0E/0F] and [BPF_AFC_ADJ_H/L:B0 0x32/33] registers for normal operation. For CCA operation, set to [BF_CCA_ADJ_H/L:B1 0x10/11] register. Following tables show coefficient value and default value corresponfding to RATE[2:0] ([DATA_SET:B0 0x47(2-0)]) setting and NBO_SEL([DATA_SET:B0 0x47(7)]) setting [When NBO_SEL=0b1] Normal operation CCA Operation Data rate [kbps] RATE[2:0] [B0 0x47] Coefficient value Default value Coefficient value Default value 50 0b000 1.44 0x034B 1.44 0x034B 100 0b01 1 0x024A 0.48 0x0119 150 0b010 0.8 0x01D4 0.497 0x0122 200 0b010 0.554 0x0144 0.36 0x00D2 400 0b011 0.343 0x00C8 0.343 0x00C8 [When NBO_SEL=0b0] Normal operation CCA Operation Data rate [kbps] RATE[2:0] [B0 0x47] Coefficient value Default value Coefficient value Default value 50 0b000 1.44 0x034B 1.44 0x034B 100 0b01 1 0x024A 1 0x024A 150 0b010 - - - - 200 0b010 0.554 0x0144 0.48 0x0119 400 0b011 - - - - [Example] Condition: Data rate is 100kbps, and [BPF_ADJ_OFFSET:B1 0x1E] =0x91 [BPF_ADJ_H/L:B1 0x0E/0F] = 0x24A + 1 * (0x11) = 0x025B [BPF_AFC_ADJ_H/L:B0 0x32/33] = 0x24A + 1 * (0x11) = 0x025B [BF_CCA_ADJ_H/L:B1 0x10/11] = 0x119 + 0.48 * (0x11) = 0x0121 Note: For 10kbps, 20kbps, 40kbps setting, please refer to the "Initial register setting" file. |
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