ML7396AB datasheet(96/140 Pages) LAPIS

96 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

96/140

●TX mode (Packet mode, packet length ≥ 257byte)

The host MCU should write TX data to a FIFO while checking FIFO-Full interrupt (INT[05] group1) and FIFO-Empty

interrupt (INT[04] group1) in order to avoid FIFO-Overrun or FIFO-Underrun. Other operation are same as packet mode (less

than 256byte).

Enabling FAST_TX mode by setting AUTO_TX ([PACKET_MODE_SET:B0 0x45(2)] =0b1 and FAST_TX_TRG[7:0]

([FAST_TX_SET:B0 0x6A(7-0)], TX will start when data amount written to a FIFO exceeds the setting value of

FAST_TX_TRG[7:0].

START

FAST_TX setting

When sending ACK request packet, please set

AUTO_RX_EN =0b1.

AUTO_TX ([PACKET_MODE_SET:B0 0x45(2)])=0b1

FAST_TX trigger: [FAST_TX_SET:B0 0x6A]

([AUTO_ACK_SET:B0 0x55(6)])

TX FIFO trigger level LH: [TX_ALARM_LH: B0 0x35]

TX FIFO trigger level HL: [TX_ALARM_HL:B0 0x36]

If data amount written to a FIFO exceeds

the FAST_TX_TRG[7:0], TX will start.

Write TX data to FIFO

[WR_TX_FIFO:B0 0x7E]

END

Clear interrupts

INT[16],[22] or INT[17].[23]

[INT_SOURCE_GRP3:B0 0x26]

Yes

FIFO-Empty (INT[04])?

[INT_SOURCE_GRP1:B0 0x24]

*Total data amount should be the size

subtracting CRC length from the

Length value.

Write TX data to FIFO

[WR_TX_FIFO:B0 0x7E]

If too much TX data written to a

FIFO, aftert TX completion interrupt,

issue TRX_OFF and then issue PHY

reset.

Clear INT[04]

[INT_SOURCE_GRP1:B0 0x24]

TX data request accept completion int?

(INT[22] or INT[23])

[INT_SOURCE_GRP3:B0 0x26]

Yes

TX completion(INT[16]/[17])?

[[INT_SOURCE_GRP3:B0 0x 26]

Go to RX flowchart

Yes

AUTO_RX_EN =0b1?

[AUTO_ACK_SET:B0 0x55(6)]

and

Send ACK request packet?

Write TX data to FIFO

[WR_TX_FIFO:B0 0x7E]

Next packet TX?

Set AUTO_TX=0b0

[PAKET_MODE_SET: B0 0x45(2)]

ML7396AB Datasheet(PDF) 96 Page - LAPIS Semiconductor Co., Ltd.

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