LP5922 datasheet(11/24 Pages) TI1

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SS/NR

LP5922

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SNVSAG0 – NOVEMBER 2016

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Feature Description (continued)

7.3.2 Enable

The LP5922 EN pin is internally held low by a 2-M

Ω resistor to GND. The EN pin voltage must be higher than the

VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must

be lower than the VIL threshold to ensure that the device is fully disabled and the automatic output discharge is

activated.

7.3.3 Output Automatic Discharge

The LP5922 output employs an internal 400-Ω (typical) pulldown resistance to discharge the output capacitor

when the EN pin is low, and the device is disabled.

7.3.4 Programmable Soft Start and Noise Reduction

The output voltage of LP5922 ramps up linearly in a constant slew rate until reaching the target regulating

voltage after a stable VIN (greater than VOUT + VDO) is supplied and EN pin is pulled high. The slew rate of VOUT

ramping is programmable by an external capacitor on the SS/NR pin; therefore, the duration for soft-start period

is programmable as well. Once the LP5922 is enabled, the SS/NR pin sources a constant 6-µA current to charge

the external CSS/NR capacitor until the voltage at the SS/NR pin reaches 98% of the internal reference voltage

(VREF) of 500 mV typical. The final 2% of CSS/NR charge is determined by a RC time constant. During the soft-

start period, the current flowing into the IN pin primarily consists of the sum of the load current at the LDO output

and the charging current into the output capacitor. The soft-start period can be calculated by Equation 2:

where

•

VFB = 0.5 V - this is the voltage that CSS/NR charges to;

•

CSS/NR is the value of the capacitor connected between the SS/NR pin and ground; and

•

ISS = 6.2 µA is the typical charging current to the SS/NR pin during start-up period.

(2)

The recommended value for CSS/NR is 100 nF or larger. Equation 2 is most accurate for these values. The CSS/NR

capacitor is also the filter capacitor for internal reference for noise reduction purpose. An integrated resistor and

the CSS/NR capacitor structure a RC low-pass filter to remove the noise on the internal reference voltage.

7.3.5 Internal Current Limit

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The

LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources

constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current

limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting

in a thermal shutdown of the output.

7.3.6 Thermal Overload Protection

Thermal shutdown disables the output when the junction temperature rises to TSD level, which allows the device

to cool. When the junction temperature cools by ΔTSD, the output circuitry enables. Based on power dissipation,

thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal

cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.

The internal protection circuitry of the LP5922 is designed to protect against thermal overload conditions. The

circuitry is not intended to replace proper heat sinking. Continuously running the LP5922 into thermal shutdown

degrades device reliability.

LP5922 Datasheet(PDF) 11 Page - Texas Instruments

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