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LP5922

SNVSAG0 – NOVEMBER 2016

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Copyright © 2016, Texas Instruments Incorporated

8.2.2 Detailed Design Procedure

8.2.2.1 External Capacitors

The LP5922 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the

input, output, and the noise-reduction pin (SS/NR). Multilayer ceramic capacitors have become the industry

standard for these types of applications and are recommended, but must be used with good judgment. Ceramic

capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability

across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in

capacitance. Additionally, the case size has a direct impact on the capacitance versus applied voltage derating.

Regardless of the ceramic capacitor type selected, the actual capacitance varies with the applied operating

voltage and temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output

capacitors recommended herein account for a effective capacitance derating of approximately 50%, but at high

applied voltage conditions the capacitance derating can be greater than 50% and must be taken into

consideration. The minimum capacitance values declared in Input and Output Capacitors must be met across the

entire expected operating voltage range and temperature range.

An input capacitor is required for stability. A capacitor with a value of at least 22 μF must be connected between

the LP5922 IN pin and ground for stable operation over full load current range. It is acceptable to have more

output capacitance than input, as long as the input is at least 22 μF.

The input capacitor must be located as close as possible to, but at a distance not more than 1 cm from, the IN

pin and returned to the device GND pin with a clean analog ground. This will minimize the trace inductance

between the capacitor and the device. Any good quality ceramic or tantalum capacitor may be used at the input.

The LP5922 is designed to work specifically with a low ESR ceramic (MLCC) output capacitor, typically 22 μF. A

ceramic capacitor (dielectric types X5R or X7R) in the 22-μF to 100-μF range, with an ESR not exceeding 500

mΩ, is suitable in the LP5922 application circuit having an output voltage greater than 0.8 V. For output voltages

of 0.8 V or less, the output capacitance must be increased to typically 47 μF. The output capacitor must be

connected between the device OUT and GND pins. The output capacitor must meet the requirement for the

minimum value of capacitance and have an ESR value that does not exceed 500 mΩ to ensure stability.

It is possible to use tantalum capacitors at the device output, but these are not as attractive for reasons of size,

cost, and performance.

A combination of multiple output capacitors in parallel boosts the high-frequency PSRR. The combination of one

0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized, 10-µF ceramic capacitors with a sufficient

voltage rating optimizes PSRR response in the frequency range of 400 kHz to 700 kHz (which is a typical range

for dc-dc supply switching frequency). This 47-µF || 10-µF || 10-µF combination also ensures that at high input

voltage and high output voltage configurations, the minimum effective capacitance is met. Many 0805-sized, 47-

µF ceramic capacitors have a voltage derating of approximately 60% to 75% at 5 V, so the addition of the two

10-µF capacitors ensures that the capacitance is at or above 22 µF.

used; however, the start-up time may be longer and the Power-Good signal may incorrectly indicate that the

output voltage is settled. The maximum recommended value is 100 nF

To ensure proper PGx functionality, the time constant defined by CNR/SSx must be greater than or equal to the

time constant from CFFx. For a detailed description, see the application report Pros and Cons of Using a Feed-

Forward Capacitor with a Low Dropout Regulator (SBVA042).