ADC08D1000EVAL datasheet(18/31 Pages) NSC

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1.0 Functional Description

The ADC08D1000 is a versatile A/D Converter with an inno-

vative architecture permitting very high speed operation. The

controls available ease the application of the device to circuit

solutions. Optimum performance requires adherence to the

provisions discussed here and in the Applications Informa-

tion Section.

While it is generally poor practice to allow an active pin to

float, pins 4, 14 and 127 of the ADC08D1000 are designed to

be left floating without jeopardy. In all discussions throughout

this data sheet, whenever a function is called by allowing a

pin to float, connecting that pin to a potential of one half the

A supply voltage will have the same effect as allowing it to

float.

1.1 OVERVIEW

The ADC08D1000 uses a calibrated folding and interpolating

architecture that achieves over 7.5 effective bits. The use of

folding amplifiers greatly reduces the number of comparators

and power consumption. Interpolation reduces the number

of front-end amplifiers required, minimizing the load on the

input signal and further reducing power requirements. In

addition to other things, on-chip calibration reduces the INL

bow often seen with folding architectures. The result is an

extremely fast, high performance, low power converter.

The analog input signal that is within the converter’s input

voltage range is digitized to eight bits at speeds of 200

MSPS to 1.6 GSPS, typical. Differential input voltages below

negative full-scale will cause the output word to consist of all

zeroes. Differential input voltages above positive full-scale

will cause the output word to consist of all ones. Either of

these conditions at either the "I" or "Q" input will cause the

OR (Out of Range) output to be activated. This single OR

output indicates when the output code from one or both of

the channels is below negative full scale or above positive

full scale.

Each of the two converters has a 1:2 demultiplexer that

feeds two LVDS output buses. The data on these buses

provide an output word rate on each bus at half the ADC

sampling rate and must be interleaved by the user to provide

output words at the full conversion rate.

The output levels may be selected to be normal or reduced.

Using reduced levels saves power but could result in erro-

neous data capture of some or all of the bits, especially at

higher sample rates and in marginally designed systems.

1.1.1 Self-Calibration

A self-calibration is performed upon power-up and can also

be invoked by the user upon command. Calibration trims the

100

Ω analog input differential termination resistor and mini-

mizes full-scale error, offset error, DNL and INL, resulting in

maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal

bias currents are also set with the calibration process. All of

this is true whether the calibration is performed upon power

up or is performed upon command. Running the self calibra-

tion is an important part of this chip’s functionality and is

required in order to obtain adequate performance. In addi-

tion to the requirement to be run at power-up, self calibration

must be re-run whenever the sense of the FSR pin is

changed. For best performance, we recommend that self

calibration be run 20 seconds or more after application of

power and whenever the operating ambient temperature

changes more than 30˚C since calibration was last per-

formed. See Section 2.4.2.2 for more information. Calibra-

tion can not be initiated or run while the device is in the

power-down mode. See Section 1.1.7 for information on the

interaction between Power Down and Calibration.

During the calibration process, the input termination resistor

is trimmed to a value that is equal to R

EXT / 33. This external

resistor is located between pin 32 and ground. R

EXT must be

3300

Ω ±0.1%. With this value, the input termination resistor

is trimmed to be 100

Ω. Because R

EXT is also used to set the

proper current for the Track and Hold amplifier, for the

preamplifiers and for the comparators, other values of R

EXT

should not be used. In normal operation, calibration is per-

formed just after application of power and whenever a valid

calibration command is given, which is holding the CAL pin

low for at least 10 input clock cycles, then hold it high for at

least another 10 input clock cycles. The time taken by the

calibration procedure is specified in the A.C. Characteristics

Table. Holding the CAL pin high upon power up will prevent

the calibration process from running until the CAL pin expe-

riences the above-mentioned 10 input clock cycles low fol-

lowed by 10 cycles high.

CalDly (pin 127) is used to select one of two delay times after

the application of power to the start of calibration. This

calibration delay is 2

25 input clock cycles (about 33.6 ms at

1 GSPS) with CalDly low, or 2

31 input clock cycles (about

2.15 seconds at 1 GSPS) with CalDly high. These delay

values allow the power supply to come up and stabilize

before calibration takes place. If the PD pin is high upon

power-up, the calibration delay counter will be disabled until

the PD pin is brought low. Therefore, holding the PD pin high

during power up will further delay the start of the power-up

calibration cycle. The best setting of the CalDly pin depends

upon the power-on settling time of the power supply.

The CalRun output is high whenever the calibration proce-

dure is running. This is true whether the calibration is done at

power-up or on-command.

1.1.2 Acquiring the Input

Data is acquired at the falling edge of CLK+ (pin 18) and the

digital equivalent of that data is available at the digital out-

puts 13 input clock cycles later for the DI and DQ output

buses and 14 input clock cycles later for the DId and DQd

output buses. There is an additional internal delay called t

before the data is available at the outputs. See the Timing

Diagram. The ADC08D1000 will convert as long as the input

clock signal is present. The fully differential comparator de-

sign and the innovative design of the sample-and-hold am-

plifier, together with self calibration, enables a very flat

SINAD/ENOB response beyond 1.0 GHz. The ADC08D1000

output data signaling is LVDS and the output format is offset

binary.

1.1.3 Control Modes

Much of the user control can be accomplished with several

control pins that are provided. Examples include initiation of

the calibration cycle, power down mode and full scale range

setting. However, the ADC08D1000 also provides an Ex-

tended Control mode whereby a serial interface is used to

access register-based control of several advanced features.

The Extended Control mode is not intended to be enabled

and disabled dynamically. Rather, the user is expected to

employ either the normal control mode or the Extended

Control mode at all times. When the device is in the Ex-

tended Control mode, pin-based control of several features

is replaced with register-based control and those pin-based

ADC08D1000EVAL Datasheet(PDF) 18 Page - National Semiconductor (TI)

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