ADC08D1000EVAL datasheet(20/31 Pages) NSC

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1.0 Functional Description (Continued)

1.1.6 The LVDS Outputs

The data outputs, the Out Of Range (OR) and DCLK, are

LVDS. Output current sources provide 3 mA of output current

to a differential 100 Ohm load when the OutV input (pin 14)

is high or 2.2 mA when the OutV input is low. For short LVDS

lines and low noise systems, satisfactory performance may

be realized with the OutV input low, which results in lower

power consumption. If the LVDS lines are long and/or the

system in which the ADC08D1000 is used is noisy, it may be

necessary to tie the OutV pin high.

1.1.7 Power Down

The ADC08D1000 is in the active state when the Power

Down pin (PD) is low. When the PD pin is high, the device is

in the power down mode, where the output pins hold the last

conversion before the PD pin went high and the device

power consumption is reduced to a minimual level. A high on

the PDQ pin will power down the "Q" channel and leave the

"I" channel active. There is no provision to power down the

"I" channel independently of the "Q" channel. Upon return to

normal operation, the pipeline will contain meaningless in-

formation.

If the PD input is brought high while a calibration is running,

the device will not go into power down until the calibration

sequence is complete. However, if power is applied and PD

is already high, the device will not begin the calibration

sequence until the PD input goes low. If a manual calibration

is requested while the device is powered down, the calibra-

tion will not begin at all. That is, the manual calibration input

is completely ignored in the power down state. Calibration

will function with the "Q" channel powered down, but that

channel will not be calibrated if PDQ is high. If the "Q"

channel is subsequently to be used, it is necessary to per-

form a calibration after PDQ is brought low.

1.2 NORMAL/EXTENDED CONTROL

The ADC08D1000 may be operated in one of two modes. In

the simpler "normal" control mode, the user affects available

configuration and control of the device through several con-

trol pins. The "extended control mode" provides additional

configuration and control options through a serial interface

and a set of 8 registers. The two control modes are selected

with pin 14 (FSR/ECE: Extended Control Enable). The

choice of control modes is required to be a fixed selection

and is not intended to be switched dynamically while the

device is operational.

Table 2 shows how several of the device features are af-

fected by the control mode chosen.

TABLE 2. Features and modes

Feature

Normal Control Mode

Extended Control Mode

SDR or DDR Clocking

Selected with pin 4

Selected with DE bit in the

Configuration Register

DDR Clock Phase

Not Selectable (0˚ Phase Only)

Selected with DCP bit in the

Configuration Register. See Section

1.4 REGISTER DESCRIPTION

SDR Data transitions with rising or

falling DCLK edge

Selected with pin 4

Selected with the OE bit in the

Configuration Register

LVDS output level

Selected with pin 3

Selected with the OV bit in the

Configuration Register

Power-On Calibration Delay

Delay Selected with pin 127

Short delay only.

Full-Scale Range

Options (600 mV

P-P or 800 mVP-P)

selected with pin 14. Selected range

applies to both channels.

Up to 512 step adjustments over a

nominal range of 560 mV to 840 mV.

Separate range selected for I- and

Q-Channels. Selected using registers

3H and Bh

Input Offset Adjust

Not possible

Separate ±45 mV adjustments in 512

steps for each channel using registers

2h and Ah

Dual Edge Sampling Selection

Enabled with pin 127

Enabled through DES Enable Register

Dual Edge Sampling Input Channel

Selection

Only I-Channel Input can be used

Either I- or Q-Channel input may be

sampled by both ADCs

DES Sampling Clock Adjustment

The Clock Phase is adjusted

automatically

Automatic Clock Phase control can be

selected by setting bit 14 in the DES

Enable register (Dh). The clock phase

can also be adjusted manually through

the Coarse & Fine registers (Eh and

Fh)

ADC08D1000EVAL Datasheet(PDF) 20 Page - National Semiconductor (TI)

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