ADC08D1000EVAL datasheet(24/31 Pages) NSC

24 / 31 page

1.0 Functional Description (Continued)

DES Fine Adjust

Addr: Fh (1111b)

W only (0x007F)

D15

D14

D13

D12

D11

D10

(MSB)

FAM

(LSB)

111111

Bits 15:7

Fine Adjust Magnitude. Each code value in

this field delays either the "I" channel or the

"Q" channel sample clock (as determined by

the ADS bit of the DES Coarse Adjust

00h in this field causes zero adjustment.

Note that the amount of adjustment achieved

with each code will vary with the device

conditions as well as with the Coarse

Adjustment value chosen.

POR State: 00h

Bit 6:0

Must be set to "1"

1.5 MULTIPLE ADC SYNCHRONIZATION

The ADC08D1000 has the capability to precisely reset its

sampling clock input to DCLK output relationship as deter-

mined by the user-supplied DCLK_RST pulse. This allows

multiple ADCs in a system to have their DCLK (and data)

outputs transition at the same time with respect to the shared

CLK input that they all use for sampling.

The DCLK_RST signal must observe some timing require-

ments that are shown in Figure 6, Figure 7 and Figure 8 of

the Timing Diagrams. The DCLK_RST pulse must be of a

minimum width and its deassertion edge must observe setup

and hold times with respect to the CLK input rising edge.

These times are specified in the AC Electrical Characteris-

tics Table.

The DCLK_RST signal can be asserted asynchronous to the

input clock. If DCLK_RST is asserted, the DCLK output is

immediately held in a designated state. The state in which

DCLK is held during the reset period is determined by the

mode of operation (SDR/DDR) and the setting of the Output

Edge configuration pin or bit. (Refer to Figure 6, Figure 7 and

Figure 8 for the DCLK reset state conditions). Therefore,

depending upon when the DCLK_RST signal is asserted,

there may be a narrow pulse on the DCLK line during this

reset event. When the DCLK_RST signal is deasserted in

synchronization with the CLK rising edge, the next CLK

falling edge synchronizes the DCLK output with those of

other ADC08D1000s in the system. The DCLK output is

enabled again after a constant delay which is equal to the

CLK input to DCLK output delay (t

AD). The device always

exhibits this delay characteristic in normal operation.

The DCLK-RST pin should NOT be brought high while the

calibration process is running (while CalRun is high). Doing

so could cause a digital glitch in the digital circuitry, resulting

in corruption and invalidation of the calibration.

2.0 Applications Information

2.1 THE REFERENCE VOLTAGE

The voltage reference for the ADC08D1000 is derived from a

1.254V bandgap reference which is made available at pin

31, V

BG for user convenience and has an output current

capability of ±100 µA and should be buffered if more current

than this is required.

The internal bandgap-derived reference voltage has a nomi-

nal value of 600 mV or 800 mV, as determined by the FSR

pin and described in Section 1.1.4.

There is no provision for the use of an external reference

voltage, but the full-scale input voltage can be adjusted

through a Configuration Register in the Extended Control

mode, as explained in Section 1.2.

Differential input signals up to the chosen full-scale level will

be digitized to 8 bits. Signal excursions beyond the full-scale

range will be clipped at the output. These large signal excur-

sions will also activate the OR output for the time that the

signal is out of range. See Section 2.2.2.

2.2 THE ANALOG INPUT

The analog input is a differential one to which the signal

source may be a.c. coupled or d.c. coupled. The full-scale

input range is selected with the FSR pin to be 600 mV

P-P or

800 mV

P-P, or can be adjusted to values between 560 mVP-P

and 840 mV

P-P in the Extended Control mode through the

Serial Interface. For best performance, it is recommended

that the full-scale range be kept between 595 mV

P-P and 805

P-P.

Table 5 gives the input to output relationship with the FSR

pin high and the normal (non-extended) mode is used. With

the FSR pin grounded, the millivolt values in Table 5 are

reduced to 75% of the values indicated. In the Enhanced

Control Mode, these values will be determined by the full

scale range and offset settings in the Control Registers.

TABLE 5. DIFFERENTIAL INPUT TO OUTPUT

RELATIONSHIP (Non-Extended Control Mode, FSR

High)

IN+VIN−

Output Code

CM − 200 mV

CM + 200 mV

0000 0000

CM −99mV

CM + 99 mV

0100 0000

0111 1111 /

1000 0000

CM + 101 mV

CM − 101 mV

1100 0000

CM + 200mV

CM − 200 mV

1111 1111

The buffered analog inputs simplify the task of driving these

inputs and the RC pole that is generally used at sampling

ADC inputs is not required. If it is desired to use an amplifier

circuit before the ADC, use care in choosing an amplifier with

adequate noise and distortion performance and adequate

gain at the frequencies used for the application.

Note that a precise d.c. common mode voltage must be

present at the ADC inputs. This common mode voltage,

CMO, is provided on-chip when a.c. input coupling is used

and the input signal is a.c. coupled to the ADC.

When the inputs are a.c. coupled, the V

CMO output must be

grounded, as shown in Figure 9. This causes the on-chip

CMO voltage to be connected to the inputs through on-chip

50k-Ohm resistors.

ADC08D1000EVAL Datasheet(PDF) 24 Page - National Semiconductor (TI)

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