[Note: This product is currently in development. As such, the parameters specified in this section are DESIGN TAR-

GETS. The specifications in this section cannot be guaranteed until device characterization has taken place.]

The following specifications apply after calibration for V

800mV

Extended Control Mode, R

T

Symbol

Parameter

Conditions

Typical

(Note 8)

Limits

(Note 8)

Units

(Limits)

DIGITAL OUTPUT CHARACTERISTICS

I

OS

Output Short Circuit Current

Output+ & Output- connected to

0.8V

−4

mA

Z

O

Differential Output Impedance

100

Ohms

POWER SUPPLY CHARACTERISTICS

I

A

Analog Supply Current

PD = PDQ = Low

PD = Low, PDQ = High

PD = High

627

325

4.3

690

360

mA (max)

mA

mA

I

DR

Output Driver Supply Current

PD = PDQ = Low

PD = Low, PDQ = High

PD = PDQ = High

202

116

1

257

135

mA (max)

mA (max)

mA

P

D

Power Consumption

PD = PDQ = Low

PD = Low, PDQ = High

PD = PDQ = High

1.6

0.84

20

1.8

0.94

W (max)

W

mW

PSRR1

D.C. Power Supply Rejection Ratio

Change in Full Scale Error with

change in V

73

dB

PSRR2

A.C. Power Supply Rejection Ratio

248 MHz, 50mV

TBD

dB

AC ELECTRICAL CHARACTERISTICS

f

CLK1

Maximum Conversion Rate

T

A

≤ 85˚C

1.1

1.0

GHz (min)

T

A

≤ 75˚C

1.3

GHz

f

CLK2

Minimum Conversion Rate

200

MHz

Input Clock Duty Cycle

200 MHz

≤ Input clock frequency ≤

1 GHz

50

20

80

% (min)

% (max)

t

CL

Input Clock Low Time

(Note 12)

500

200

ps (min)

t

CH

Input Clock High Time

(Note 12)

500

200

ps (min)

DCLK Duty Cycle

(Note 12)

50

45

55

% (min)

% (max)

t

RS

Reset Setup Time

(Note 12)

150

TBD

ps (min)

t

RH

Reset Hold Time

(Note 12)

250

TBD

ps (min)

t

RPW

Reset Pulse Width

4

Clock Cycles

(min)

t

LHT

Differential Low to High Transition

Time

10% to 90%, C

250

ps

t

HLT

Differential High to Low Transition

Time

10% to 90%, C

250

ps

t

OSK

DCLK to Data Output Skew

50% of DCLK transition to 50% of

Data transition, SDR Mode

and DDR Mode, 0˚ DCLK (Note 12)

ps (max)

t

SU

Data to DCLK Set-Up Time

DDR Mode, 180˚ DCLK (Note 12)

750

TBD

ps (min)

t

H

DCLK to Data Hold Time

DDR Mode, 180˚ DCLK (Note 12)

750

TBD

ps (min)

t

AD

Sampling (Aperture) Delay

Input CLK+ Fall to Acquisition of

Data

1.3

ns

t

AJ

Aperture Jitter

0.4

ps rms

t

OD

Input Clock to Data Output Delay

50% of Input Clock transition to

50% of Data transition

3.1

ns

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