ADC08D1000EVAL datasheet(26/31 Pages) NSC

26 / 31 page

2.0 Applications Information

(Continued)

The differential input clock line pair should have a character-

istic impedance of 100

Ω and be terminated at the clock

source in that (100

Ω) characteristic impedance. The input

clock line should be as short and as direct as possible. The

ADC08D1000 clock input is internally terminated with an

untrimmed 100

Ω resistor.

Insufficient input clock levels will result in poor dynamic

performance. Excessively high input clock levels could

cause a change in the analog input offset voltage. To avoid

these problems, keep the input clock level within the range

specified in the Electrical Characteristics Table.

The low and high times of the input clock signal can affect

the performance of any A/D Converter. While it is specified

and performance is guaranteed at 1.0 GSPS with a 50%

input clock duty cycle, ADC08D1000 performance is typically

maintained over temperature if the input clock high and low

times are maintained within the range specified in the Elec-

trical Characteristics Table.

High

speed,

high

performance

ADCs

such

the

ADC08D1000 require a very stable input clock signal with

minimum phase noise or jitter. ADC jitter requirements are

defined by the ADC resolution (number of bits), maximum

ADC input frequency and the input signal amplitude relative

to the ADC input full scale range. The maximum jitter (the

sum of the jitter from all sources) allowed to prevent a

jitter-induced reduction in SNR is found to be

J(MAX) =(VIN(P-P)/VINFSR) x (1/(2

(N+1) x

π xf

IN))

where t

J(MAX) is the rms total of all jitter sources in seconds,

IN(P-P) is the peak-to-peak analog input signal, VINFSR is the

full-scale range of the ADC, "N" is the ADC resolution in bits

and f

IN is the maximum input frequency, in Hertz, to the ADC

analog input.

Note that the maximum jitter described above is the arith-

metic sum of the jitter from all sources, including that in the

ADC input clock, that added by the system to the ADC input

clock and input signals and that added by the ADC itself.

Since the effective jitter added by the ADC is beyond user

control, the best the user can do is to keep the sum of the

externally added input clock jitter and the jitter added by the

analog circuitry to the analog signal to a minimum.

Input clock amplitudes above those specified in the Electrical

Characteristics Table may result in increased input offset

voltage. This would cause the converter to produce an out-

put code other than the expected 127/128 when both input

pins are at the same potential.

2.4 CONTROL PINS

Six control pins (without the use of the serial interface)

provide a wide range of possibilities in the operation of the

ADC08D1000 and facilitate its use. These control pins pro-

vide Full-Scale Input Range setting, Self Calibration, Calibra-

tion Delay, Output Edge Synchronization choice, LVDS Out-

put Level choice and a Power Down feature.

2.4.1 Full-Scale Input Range Setting

The input full-scale range can be selected to be either 600

P-P or 800 mVP-P, as selected with the FSR control input

(pin 14) in the Normal Mode of operation. In the Extended

Control Mode, the input full-scale range may be set to be

anywhere from 560 mV

P-P to 840 mVP-P. See Section 2.2 for

more information.

2.4.2 Self Calibration

The ADC08D1000 self-calibration must be run to achieve

specified performance. The calibration procedure is run

upon power-up and can be run any time on command. The

calibration procedure is exactly the same whether there is an

input clock present upon power up or if the clock begins

some time after application of power. The CalRun output

indicator is high while a calibration is in progress.

2.4.2.1 Power-On Calibration

Power-on calibration begins after a time delay following the

application of power. This time delay is determined by the

setting of CalDly, as described in the Calibration Delay Sec-

tion, below.

The calibration process will be not be performed if the CAL

pin is high at power up. In this case, the calibration cycle will

not begin until the on-command calibration conditions are

met. The ADC08D1000 will function with the CAL pin held

high at power up, but no calibration will be done and perfor-

mance will be impaired. A manual calibration, however, may

be performed after powering up with the CAL pin high. See

On-Command Calibration Section 2.4.2.2.

The internal power-on calibration circuitry comes up in a

random state. If the input clock is not running at power up

and the power on calibration circuitry is active, it will hold the

analog circuitry in power down and the power consumption

will typically be less than 200 mW. The power consumption

will be normal after the clock starts.

2.4.2.2 On-Command Calibration

Calibration may be run at any time by bringing the CAL pin

high for a minimum of 10 input clock cycles after it has been

low for a minimum of 10 input clock cycles. Holding the CAL

pin high upon power up will prevent execution of power-on

calibration until the CAL pin is low for a minimum of 10 input

clock cycles, then brought high for a minimum of another 10

input clock cycles. The calibration cycle will begin 10 input

clock cycles after the CAL pin is thus brought high.

The minimum 10 input clock cycle sequences are required to

ensure that random noise does not cause a calibration to

begin when it is not desired. As mentioned in section 1.1 for

best performance, a self calibration should be performed 20

seconds or more after power up and repeated when the

ambient temperature changes more than 30˚C since the last

self calibration was run. SINAD drops about 1.5 dB for every

30˚C change in die temperature and ENOB drops about 0.25

bit for every 30˚C change in die temperature.

20097447

FIGURE 12. Differential (LVDS) Input Clock Connection

ADC08D1000EVAL Datasheet(PDF) 26 Page - National Semiconductor (TI)

ADC08D1000EVAL Datasheet(HTML) 26 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL