ADC08D1000EVAL datasheet(29/31 Pages) NSC

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2.0 Applications Information

(Continued)

Since a large aperture opening may result in poor release,

the aperture opening should be subdivided into an array of

smaller openings, similar to the land pattern of Figure 14.

To minimize junction temperature, it is recommended that a

simple heat sink be built into the PCB. This is done by

including a copper area of about 2 square inches (6.5 square

cm) on the opposite side of the PCB. This copper area may

be plated or solder coated to prevent corrosion, but should

not have a conformal coating, which could provide some

thermal insulation. Thermal vias should be used to connect

these top and bottom copper areas. These thermal vias act

as "heat pipes" to carry the thermal energy from the device

side of the board to the opposite side of the board where it

can be more effectively dissipated. The use of 9 to 16

thermal vias is recommended.

The thermal vias should be placed on a 1.2 mm grid spacing

and have a diameter of 0.30 to 0.33 mm. These vias should

be barrel plated to avoid solder wicking into the vias during

the soldering process as this wicking could cause voids in

the solder between the package exposed pad and the ther-

mal land on the PCB. Such voids could increase the thermal

resistance between the device and the thermal land on the

board, which would cause the device to run hotter.

If it is desired to monitor die temperature, a temperature

sensor may be mounted on the heat sink area of the board

near the thermal vias. .Allow for a thermal gradient between

the temperature sensor and the ADC08D1000 die of

times typical power consumption = 2.8 x 1.6 = 4.5˚C. Allow-

ing for a 5.5˚C (including an extra 1˚C) temperature drop

from the die to the temperature sensor, then, would mean

that maintaining a maximum pad temperature reading of

124.5˚C will ensure that the die temperature does not ex-

ceed 130˚C, assuming that the exposed pad of the

ADC08D1000 is properly soldered down and the thermal

vias are adequate. (The inaccuracy of the temperature sen-

sor is addtional to the above calculation).

2.7 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are es-

sential to ensure accurate conversion. A single ground plane

should be used, as apposed to splitting the ground plane into

analog and digital areas.

Since digital switching transients are composed largely of

high frequency components, the skin effect tells us that total

ground plane copper weight will have little effect upon the

logic-generated noise. Total surface area is more important

than is total ground plane volume. Coupling between the

typically noisy digital circuitry and the sensitive analog cir-

cuitry can lead to poor performance that may seem impos-

sible to isolate and remedy. The solution is to keep the

analog circuitry well separated from the digital circuitry.

High power digital components should not be located on or

near any linear component or power supply trace or plane

that services analog or mixed signal components as the

resulting common return current path could cause fluctuation

in the analog input “ground” return of the ADC, causing

excessive noise in the conversion result.

Generally, we assume that analog and digital lines should

cross each other at 90˚ to avoid getting digital noise into the

analog path. In high frequency systems, however, avoid

crossing analog and digital lines altogether. The input clock

lines should be isolated from ALL other lines, analog AND

digital. The generally accepted 90˚ crossing should be

avoided as even a little coupling can cause problems at high

frequencies. Best performance at high frequencies is ob-

tained with a straight signal path.

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. This is

especially important with the low level drive required of the

ADC08D1000. Any external component (e.g., a filter capaci-

tor) connected between the converter’s input and ground

should be connected to a very clean point in the analog

ground plane. All analog circuitry (input amplifiers, filters,

etc.) should be separated from any digital components.

2.8 DYNAMIC PERFORMANCE

The ADC08D1000 is a.c. tested and its dynamic perfor-

mance is guaranteed. To meet the published specifications

and avoid jitter-induced noise, the clock source driving the

CLK input must exhibit low rms jitter. The allowable jitter is a

function of the input frequency and the input signal level, as

described in Section 2.3.

It is good practice to keep the ADC input clock line as short

as possible, to keep it well away from any other signals and

to treat it as a transmission line. Other signals can introduce

jitter into the input clock signal. The clock signal can also

introduce noise into the analog path if not isolated from that

path.

Best dynamic performance is obtained when the exposed

pad at the back of the package has a good connection to

ground. This is because this path from the die to ground is a

lower impedance than offered by the package pins.

2.9 USING THE SERIAL INTERFACE

The ADC08D1000 may be operated in the non-extended

control (non-Serial Interface) mode or in the extended con-

trol mode. Table 6 and Table 7 describe the functions of pins

3, 4, 14 and 127 in the non-extended control mode and the

extended control mode, respectively.

2.9.1 Non-Extended Control Mode Operation

Non-extended control mode operation means that the Serial

Interface is not active and all controllable functions are con-

trolled with various pin settings. That is, the full-scale range,

single-ended or differential input and input coupling (a.c. or

d.c.) are all controlled with pin settings. The non-extended

control mode is used by setting pin 14 high or low, as

opposed to letting it float. Table 6 indicates the pin functions

of the ADC08D1000 in the non-extended control mode.

20097421

FIGURE 14. Recommended Package Land Pattern

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