ADC08D1000EVAL datasheet(27/31 Pages) NSC

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2.0 Applications Information

(Continued)

2.4.2.3 Calibration Delay

The CalDly input (pin 127) is used to select one of two delay

times after the application of power to the start of calibration,

as described in Section 1.1.1. The calibration delay values

allow the power supply to come up and stabilize before

calibration takes place. With no delay or insufficient delay,

calibration would begin before the power supply is stabilized

at its operating value and result in non-optimal calibration

coefficients. If the PD pin is high upon power-up, the calibra-

tion delay counter will be disabled until the PD pin is brought

low. Therefore, holding the PD pin high during power up will

further delay the start of the power-up calibration cycle. The

best setting of the CalDly pin depends upon the power-on

settling time of the power supply.

Note that the calibration delay selection is not possible in the

Extended Control mode and the short delay time is used.

2.4.3 Output Edge Synchronization

DCLK signals are available to help latch the converter output

data into external circuitry. The output data can be synchro-

nized with either edge of these DCLK signals. That is, the

output data transition can be set to occur with either the

rising edge or the falling edge of the DCLK signal, so that

either edge of that DCLK signal can be used to latch the

output data into the receiving circuit.

When OutEdge (pin 4) is high, the output data is synchro-

nized with (changes with) the rising edge of the DCLK+ (pin

82). When OutEdge is low, the output data is synchronized

with the falling edge of DCLK+.

At the very high speeds of which the ADC08D1000 is ca-

pable, slight differences in the lengths of the DCLK and data

lines can mean the difference between successful and erro-

neous data capture. The OutEdge pin is used to capture

data on the DCLK edge that best suits the application circuit

and layout.

2.4.4 LVDS Output Level Control

The output level can be set to one of two levels with OutV

(pin3). The strength of the output drivers is greater with OutV

high. With OutV low there is less power consumption in the

output drivers, but the lower output level means decreased

noise immunity.

For short LVDS lines and low noise systems, satisfactory

performance may be realized with the FSR input low. If the

LVDS lines are long and/or the system in which the

ADC08D1000 is used is noisy, it may be necessary to tie the

FSR pin high.

2.4.5 Dual Edge Sampling

The Dual Edge Sampling (DES) feature causes one of the

two input pairs to be routed to both ADCs. The other input

pair is deactivated. One of the ADCs samples the input

signal on one input clock edge, the other samples the input

signal on the other input clock edge. The result is a 4:1

demultiplexed output with a sample rate that is twice the

input clock frequency.

To use this feature in the non-enhanced control mode, allow

pin 127 to float and the signal at the "I" channel input will be

sampled by both converters. The Calibration Delay will then

only be a short delay.

In the enhanced control mode, either input may be used for

dual edge sampling. See Section 1.1.5.1.

IMPORTANT NOTE :

When using the Automatic Clock Phase Control feature in

dual edge sampling mode, it is important that the automatic

phase control is disabled (set bit 14 of DES Enable register

Dh to 0) before the ADC is powered down. Not doing so may

cause the device not to wakeup from the powerdown state.

The automatic phase control should also be disabled if the

input clock is intrerrupted for any reason, or a large abrupt

change in the clock frequency occurs.

Also when the ADC08D1000 is powered up and DES mode

is required, ensure that pin 127 (CalDly/DES/notSCS) is

initially pulled low during or after the power up sequence.

The pin can then be allowed to float or be tied to VCC/2 to

enter the DES mode. This will ensure that the part enters the

DES mode correctly.

2.4.6 Power Down Feature

The

Power

Down

pins

(PD

and

PDQ)

allow

the

ADC08D1000 to be entirely powered down (PD) or the "Q"

channel to be powered down and the "I" channel to remain

active. See Section 1.1.7 for details on the power down

feature.

The digital output pins retain the last conversion output code

when either the input clock is stopped or the PD pin is high.

However, upon return to normal operation, the pipeline will

contain meaningless information and must be flushed.

If the PD input is brought high while a calibration is running,

the device will not go into power down until the calibration

sequence is complete. However, if power is applied and PD

is already high, the device will not begin the calibration

sequence until the PD input goes low. If a manual calibration

is requested while the device is powered down, the calibra-

tion will not begin at all. That is, the manual calibration input

is completely ignored in the power down state.

2.5 THE DIGITAL OUTPUTS

The ADC08D1000 demultiplexes the output data of each of

the two ADCs on the die onto two LVDS output buses (total

of four buses, two for each ADC). For each of the two

converters, the results of successive conversions started on

the odd falling edges of the CLK+ pin are available on one of

the two LVDS buses, while the results of conversions started

on the even falling edges of the CLK+ pin are available on

the other LVDS bus. This means that, in the SDR mode, the

word rate at each LVDS bus is 1/2 the ADC08D1000 input

clock rate and the two buses must be multiplexed to obtain

the entire 1 GSPS conversion result.

DDR (Double Data Rate) clocking can also be used. In this

mode a word of data is presented with each edge of DCLK,

reducing the DCLK frequency to 1/4 the input clock fre-

quency. See the Timing Diagram section for details.

Since the minimum recommended input clock rate for this

device is 200 MSPS, the effective rate can be reduced to as

low as 100 MSPS by using the results available on just one

of the the two LVDS buses and a 200 MHz input clock,

decimating the 200 MSPS data by two.

There is one LVDS output clock pair (DCLK) available for

use to latch the LVDS outputs on all buses. Whether the data

is sent at the rising or falling edge of DCLK is determined by

the sense of the OutEdge pin, as described in Section 2.4.3.

The OutV pin is used to set the LVDS differential output

levels. See Section 2.4.4.

The output format is Offset Binary. Accordingly, a full-scale

input level with V

IN+ positive with respect to VIN− will pro-

duce an output code of all ones, a full-scale input level with

ADC08D1000EVAL Datasheet(PDF) 27 Page - National Semiconductor (TI)

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