MPC823 datasheet(31/74 Pages) MOTOROLA

31 / 74 page

Communication Processor Module

MOTOROLA

MPC823 REFERENCE MANUAL

16-409

If both the REN and TEN bits are set in the SMCMR, the first falling edge of the SMSYNx

pin causes both the transmitter and receiver to achieve synchronization. To resynchronize

the transmitter or receiver, the SMCx transmitter/receiver can be disabled and reenabled

and the SMSYNx pin can be used again to resynchronize the transmitter or receiver. Refer

to Section 16.11.5 Disabling the SMCs On-the-Fly for a description of how to safely

disable and reenable a serial management controller. Simply clearing and setting the TEN

bit may not be sufficient.

Figure 16-118. SMSYNx Pin Synchronization

SMRXD

SMC1 RECEIVE DATA

SMTXD

SMSYNx

SMCLK

TEN

SET

HERE

TX FIFO

LOADED

APPX.

HERE

SMSYNx

DETECTED

LOW HERE

SMCLK

SMSYNx

REN SET

HERE OR

ENTER

HUNT MODE

COMMAND

ISSUED

FIRST BIT OF

RECEIVE

DATA (LSB)

1s ARE SENT

SMSYNx

DETECTED

LOW HERE

SMC1 TRANSMIT DATA

FIRST BIT OF

FIRST 5-BIT

TRANSMIT

CHARACTER

(LSB)

NOTES:

1. SMCLK is an internal clock derived from an external clock pin or a baud rate generator.

2. This example shows the SMC receiver and transmitter enabled separately. If the REN

and TEN bits were set at the same time, a single falling edge of SMSYNx would

synchronize both.

FIVE 1s

ASSUME

CHARACTER

LENGTH

EQUALS 5

TRANSMISSION

COULD BEGIN

HERE IF TX FIFO

NOT LOADED IN

TIME

FIVE 1s ARE SENT

MPC823 Datasheet(PDF) 31 Page - Motorola, Inc

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