MPC823 datasheet(41/74 Pages) MOTOROLA

41 / 74 page

Communication Processor Module

MOTOROLA

MPC823 REFERENCE MANUAL

16-419

16.11.7.12 SMCx TRANSPARENT EVENT REGISTER. When a serial management

controller is in transparent mode, the 8-bit memory-mapped SMCx event register is referred

to as the SMCx transparent event (SMCE–Transparent) register. It is used to generate

interrupts and report events recognized by the SMCx channel. When an event is recognized,

the serial management controller sets the corresponding bit in this register. Interrupts

generated by this register can be masked in the SMCM–Transparent register.

A bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be

cleared at a time. All unmasked bits must be cleared before the communication processor

module clears the internal interrupt request. This register is cleared at reset and can be read

at any time.

Bits 0–2 and 4—Reserved

These bits are reserved and must be set to 0.

TXE—TX Error

This bit indicates that an underrun error has occurred on the transmitter channel.

BSY—Busy Condition

This bit indicates that a character has been received and discarded due to a lack of buffers.

Reception begins after a new buffer is provided. You can execute an ENTER HUNT MODE

command to make the receiver wait for resynchronization.

TX—TX Buffer

This bit indicates that a buffer has been transmitted. If the L bit of the TX buffer descriptor is

set, this bit is set when the last data character starts being transmitted and you must wait

one character time to be sure that the data is completely sent over the transmit pin. If the L

bit of the TX buffer descriptor is cleared, this bit is set when the last data character is written

to the transmit FIFO and you must wait two character times to be sure that the data is

completely sent over the transmit pin.

RX—RX Buffer

This bit indicates that a data buffer has been received on the SMCx channel and its

associated RX buffer descriptor is now closed. This bit is set after the last character is written

to the buffer.

SMCE–TRANSPARENT

BIT

FIELD

RESERVED

TXE

RES

BSY

RESET

00000

R/W

ADDR

(IMMR & 0xFFFF0000) + 0xA86 (SMC1), 0xA96 (SMC2)

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