MPC823 datasheet(29/74 Pages) MOTOROLA

29 / 74 page

Communication Processor Module

MOTOROLA

MPC823 REFERENCE MANUAL

16-407

Synchronization can be achieved in two ways. First, when the transmitter is connected to

the TDM channel, it can be synchronized to a time-slot. Once the frame sync is received,

the transmitter waits for the first bit of its time-slot to occur before it starts transmitting. Data

is only transmitted during the time-slots defined by the time-slot assigner. Secondly, when

working with its own set of pins, the transmitter starts transmitting when the SMSYNx signal

is asserted.

When buffer descriptor data is completely written to the transmit FIFO, the L bit is checked

and if it is set, a serial management controller writes the message status bits into the buffer

descriptor and clears the R bit. It then starts transmitting idles. When the end of the current

buffer descriptor is reached and the L bit is not set, only the R bit is cleared. In both cases,

an interrupt is issued according to the I bit in the buffer descriptor. By appropriately setting

the I bit in each buffer descriptor, interrupts can be generated after each buffer, a specific

buffer, or each block is transmitted. The serial management controller then proceeds to the

next buffer descriptor in the table. If no additional buffers have been presented to the serial

management controller for transmission and the L bit was cleared, an underrun is detected

and the serial management controller begins transmitting idles.

If the CM bit is set in the transmit buffer descriptor, the R bit is not cleared, thus allowing the

associated data buffer to be automatically retransmitted next time the communication

processor module accesses this data buffer. For instance, if a single transmit buffer

descriptor is initialized with the CM bit and the W bit set, the data buffer is continuously

transmitted until you clear the R bit of the buffer descriptor.

16.11.7.3 SMCx TRANSPARENT CHANNEL RECEPTION PROCESS. When the core

enables the SMCx receiver in transparent mode, it waits for synchronization before

receiving data. Once synchronization is achieved, the receiver transfers incoming data into

memory according to the first receive buffer descriptor in the ring. Synchronization can be

achieved in two ways. First, when the receiver is connected to the TDM channel, it can be

synchronized to a time-slot. Once the frame sync is received, the receiver waits for the first

bit of its time-slot to occur before reception begins. Data is only received during the

time-slots defined by the time-slot assigner. Secondly, when working with its own set of pins,

the receiver starts receiving when the SMSYNx signal is asserted.

When the data buffer is filled, a SMCx Transparent controller clears the E bit in the buffer

descriptor and generates an interrupt if the I bit in the buffer descriptor is set. If the incoming

data exceeds the length of the data buffer, a serial management controller fetches the next

buffer descriptor in the table and, if it is empty, continues transferring data to the associated

data buffer. If the CM bit is set in the receive buffer descriptor, the E bit is not cleared, thus

allowing the associated data buffer to be automatically overwritten next time the

communication processor module accesses this data buffer.

MPC823 Datasheet(PDF) 29 Page - Motorola, Inc