MPC823 datasheet(64/74 Pages) MOTOROLA

64 / 74 page

Communication Processor Module

16-442

MPC823 REFERENCE MANUAL

MOTOROLA

PM—Prescale Modulus Select

This field specifies the divide ratio of the prescale divider in the SPI clock generator. The

BRGCLK is divided by 4 * ([PM0–PM3] + 1), thus giving a clock divide ratio of 4 to 64. The

clock has a 50% duty cycle.

16.12.4.1.1 SPI Examples With Different LEN Values. The programming examples

below illustrate the effect of the LEN field and the REV bit in the SPMODE register on output

from the SPI controller. They illustrate the master mode output from the SPI controller as the

LEN varies. To help map the output process, make

g through v the binary symbols, use x to

indicate a deleted bit, use __ to indicate original byte boundaries, and use _ to indicate

original nibble (4-bit) boundaries.

The initial pattern for all examples is ghij_klmn__opqr_stuv.

Example 1

LEN = 0x4

(Data Size = 5)

Data Selected:

xxxj_klmn_xxxr_stuv

Data Transmitted for REV=0:

nmlk_j__vuts_r

Data Transmitted for REV=1:

j_nmlk__r_stuv

Example 2

LEN = 0x7

(Data Size = 8)

Data Selected:

ghij_klmn_opqr_stuv

Data Transmitted for REV=0:

nmlk_jihg__vuts_rqpo

Data Transmitted for REV=1:

ghij_klmn__opqr_stuv

Example 3

LEN = 0xc

(Data Size = 13)

Data Selected:

ghij_klmn_xxxr_stuv

Data Transmitted for REV=0:

nmlk_jihg__vuts_r

Data Transmitted for REV=1:

r_stuv__ghij_klmn

Example 4

LEN = 0xf

(Data Size = 16)

Data Selected:

ghij_klmn_opqr_stuv

Data Transmitted for REV=0:

nmlk_jihg__vuts_rqpo

Data Transmitted for REV=1:

opqr_stuv__ghij_klmn

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