AD9528BCPZ datasheet(36/68 Pages) AD

36 / 68 page

Data Sheet

AD9528

Rev. C | Page 35 of 67

SERIAL CONTROL PORT

The AD9528 serial control port is a flexible, synchronous serial

communications port that provides a convenient interface to

many industry-standard microcontrollers and microprocessors.

The AD9528 serial control port is compatible with most

synchronous transfer formats, including I2C, Motorola SPI, and

Intel SSR protocols. The serial control port allows read/write

access to the AD9528 register map.

The AD9528 uses the Analog Devices unified SPI protocol. The

unified SPI protocol guarantees that all new Analog Devices

products using the unified protocol have consistent serial port

characteristics. The SPI port configuration is programmable via

rather than in the register map and is distinct from the I2C

Unified SPI differs from the SPI port found on older products

like the AD9523 and AD9524 in the following ways:

•

Unified SPI does not have byte counts. A transfer is

terminated when the CS pin goes high. The W1 and W0

bits in the traditional SPI become the A12 and A13 bits of

the register address. This is similar to streaming mode in

the traditional SPI.

•

The address ascension bit (Register 0x0000, Bit 2 and Bit 5)

controls whether register addresses are automatically

incremented or decremented regardless of the LSB/MSB

first setting. In traditional SPI, LSB first dictated auto-

increments and MSB first dictated autodecrements of the

•

Devices that adhere to the unified serial port have a

consistent structure of the first 16 register addresses.

Although the AD9528 supports both the SPI and I2C serial port

protocols, only one is active following power-up (as determined

by the STATUS0/SP0 and STATUS1/SP1 multifunction pins

during the start-up sequence). The only way to change the serial

port protocol is to reset (or power cycle) the device.

SPI/I2C PORT SELECTION

The AD9528 has two serial interfaces, SPI and I2C. Users can

select either the SPI or I2C depending on the states (logic high,

logic low) of the two logic level input pins (STATUS0/SP0 and

STATUS1/SP1), when initial power is applied or after a RESET.

When both STATUS/SP1 and STATUS0/SP0 are low, the SPI

interface is active. Otherwise, I2C is active with three different

I2C slave address settings (seven bits wide), as shown in Table 24.

The five most significant bits (MSBs) of the slave address are

hardware coded as 10101, and the two LSBs are determined by

the logic levels of the STATUS1/SP1and STATUS0/SP0 pins.

Table 24. Serial Port Mode Selection

STATUS1/SP1

STATUS0/SP0

Address

Low

SPI

Low

High

I2C = 1010100

High

Low

I2C = 1010101

SPI SERIAL PORT OPERATION

Pin Descriptions

The SCLK (serial clock) pin serves as the serial shift clock. This

pin is an input. SCLK synchronizes serial control port read and

write operations. The rising edge SCLK registers write data bits,

and the falling edge registers read data bits. The SCLK pin

supports a maximum clock rate of 50 MHz.

The SPI port supports both 3-wire (bidirectional) and 4-wire

(unidirectional) hardware configurations and both MSB-first

and LSB-first data formats. Both the hardware configuration

and data format features are programmable. The 3-wire mode

uses the SDIO (serial data input/output) pin for transferring

data in both directions. The 4-wire mode uses the SDIO pin for

transferring data to the AD9528, and the SDO pin for

transferring data from the AD9528.

The CS (chip select) pin is an active low control that gates read

and write operations. Assertion (active low) of the CS pin

initiates a write or read operation to the AD9528 SPI port. Any

number of data bytes can be transferred in a continuous stream.

The register address is automatically incremented or decremented

based on the setting of the address ascension bits (Register 0x0000,

Bit 2 and Bit 5). CS must be deasserted at the end of the last byte

transferred, thereby ending the stream mode. This pin is

internally connected to a 10 kΩ pull-up resistor. When CS is

high, the SDIO and SDO pins go into a high impedance state.

Implementation Specific Details

The following product specific items are defined in the unified

SPI protocol:

•

Analog Devices unified SPI protocol Revision: 1.0

•

Chip type: 0x5

•

Clock serial ID: 0x00F

•

Physical layer: 3-and 4-wire supported

•

Optional single-byte instruction mode: not supported

•

Data link not used

•

Control not used

AD9528BCPZ Datasheet(PDF) 36 Page - Analog Devices

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