AD9528BCPZ datasheet(62/68 Pages) AD

62 / 68 page

Data Sheet

AD9528

Rev. C | Page 61 of 67

Table 60. SYSREF Bypass Resample Control

Address

Bits

Bit Name

Description

0x032D

Channel 6 bypass SYSREF resample

0 = not bypassed.

1 = Channel 6 bypass SYSREF resample.

Channel 5 bypass SYSREF resample

0 = not bypassed.

1 = Channel 5 bypass SYSREF resample.

Channel 4 bypass SYSREF resample

0 = not bypassed.

1 = Channel 4 bypass SYSREF resample.

Channel 3 bypass SYSREF resample

0 = not bypassed.

1 = Channel 3 bypass SYSREF resample.

Channel 2 bypass SYSREF resample

0 = not bypassed.

1 = Channel 2 bypass SYSREF resample.

Channel 1 bypass SYSREF resample

0 = not bypassed.

1 = Channel 1 bypass SYSREF resample.

Channel 0 bypass SYSREF resample

0 = not bypassed.

1 = Channel 0 bypass SYSREF resample.

Enable VCXO receiver path to distribution

0 = path disabled.

1 = enables path.

0x032E

Reserved

Reserved.

Channel 13 bypass SYSREF resample

0 = not bypassed.

1 = Channel 13 bypass SYSREF resample.

Channel 12 bypass SYSREF resample

0 = not bypassed.

1 = Channel 12 bypass SYSREF resample.

Channel 11 bypass SYSREF resample

0 = not bypassed.

1 = Channel 11 bypass SYSREF resample.

Channel 10 bypass SYSREF resample

0 = not bypassed.

1 = Channel 10 bypass SYSREF resample.

Channel 9 bypass SYSREF resample

0 = not bypassed.

1 = Channel 9 bypass SYSREF resample.

Channel 8 bypass SYSREF resample

0 = not bypassed.

1 = Channel 8 bypass SYSREF resample.

Channel 7 bypass SYSREF resample

0 = not bypassed.

1 = Channel 7 bypass SYSREF resample.

Table 61. SYSREF Pattern Generator K Divider

Address

Bits

Bit Name

Description

0x0400,

0x0401

[7:0],

[15:8]

K divider

The 16-bit K divider divides the input clock to the SYSREF pattern generator to

program the SYSREF pulse width. Bits[7:0] are the LSB byte, and Bits[15:8] are the

MSB byte.

AD9528BCPZ Datasheet(PDF) 62 Page - Analog Devices

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