AD9528BCPZ datasheet(40/68 Pages) AD

40 / 68 page

Data Sheet

AD9528

Rev. C | Page 39 of 67

When all the data bytes are read or written, stop conditions are

established. In write mode, the master (transmitter) asserts a

stop condition to end data transfer during the clock pulse

following the acknowledge bit for the last data byte from the

slave device (receiver). In read mode, the master device

(receiver) receives the last data byte from the slave device

(transmitter) but does not pull SDA low during the ninth clock

pulse. This is known as a no acknowledge bit. By receiving the

no acknowledge bit, the slave device knows that the data

transfer is finished and enters idle mode. The master then pulls

the data line low during the low period before the 10th clock

pulse, and high during the 10th clock pulse to assert a stop

condition.

A start condition can be used in place of a stop condition.

Furthermore, a start or stop condition can occur at any time,

and partially transferred bytes are discarded.

Figure 47. Start and Stop Conditions

Figure 48. Acknowledge Bit

Figure 49. Data Transfer Process (Master Write Mode, 2-Byte Transfer)

Figure 50. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First ACK From Slave

SDA

START CONDITION

STOP CONDITION

SCL

3 TO 7

SDA

SCL

MSB

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

3 TO 7

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

SDA

SCL

MSB

3 TO 7

ACK FROM

MASTER RECEIVER

NONACK FROM

MASTER RECEIVER

SDA

SCL

AD9528BCPZ Datasheet(PDF) 40 Page - Analog Devices

AD9528BCPZ Datasheet(HTML) 40 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL