AD9528BCPZ datasheet(55/68 Pages) AD

55 / 68 page

AD9528

Data Sheet

Rev. C | Page 54 of 67

PLL1 CONTROL (REGISTER 0x0100 TO REGISTER 0x010B)

Table 43. PLL1 REFA Divider (RA) and REFB Divider (RB) Control

Address

Bits

Bit Name

Description

0x0100

[7:0]

10-bit REFA (R

A) divider

10-bit REFA divider, Bits[7:0] (LSB). Divide by 1 to divide by 1023.

0000000000, 0000000001 = divide by 1.

0x0101

[1:0]

10-bit REFA divider, Bits[9:8] (MSB).

0x0102

[7:0]

10-bit REFB (R

B) divider

10-bit REFB divider, Bits[7:0] (LSB). Divide by 1 to divide by 1023.

0000000000, 0000000001 = divide by 1.

0x0103

[1:0]

10-bit REFB divider, Bits[9:8] (MSB).

Table 44. PLL1 Feedback Divider (N1)

Address

Bits

Bit Name

Description

0x0104

[7:0]

10-bit N1 divider

10-bit feedback divider, Bits[7:0] (LSB). Divide by 1 to divide by 1023.

0000000000, 0000000001 = divide by 1.

0x0105

[1:0]

10-bit feedback divider, Bits[9:8] (MSB).

Table 45. PLL1 Charge Pump Control

Address

Bits

Bit Name

Description

0x0106

Force holdover

Tristates the PLL1 charge pump.

0 = normal operation.

1 = forces holdover.

[6:0]

PLL1 charge pump current (μA),

Bits[6:0]

These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 μA

with a full-scale magnitude of ~63.5 μA.

0x0107

[7:6]

Reserved

Reserved.

Disable holdover

Disable automatic holdover.

0 = automatic holdover enabled.

1 = automatic holdover disabled.

[4:2]

Reserved

Reserved.

[1:0]

Charge pump mode, Bits[1:0]

Controls the mode of the PLL1 charge pump.

00 = tristate (default).

01 = pump down.

10 = pump up.

11 = normal.

AD9528BCPZ Datasheet(PDF) 55 Page - Analog Devices

AD9528BCPZ Datasheet(HTML) 55 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL