WTS701MFSLASHT datasheet(16/77 Pages) WINBOND

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WTS701

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7.2.5 Flow Control Interface

In addition to the SPI interface, the WTS701 has two control lines to facilitate data transfer and host

communications. The INT

(interrupt) pin is used by the WTS701 to request an interrupt service

from the host controller. The interrupt types that the device generates are controlled by the

communications control register command (SCOM). The R/ B (ready/busy) pin is used to control the

flow of data across the SPI bus. When this signal is HIGH, the device can accept more data. When it

is LOW, SPI transactions must be paused or terminated.

INT

(Interrupt)

INT

is an open drain output pin. The WTS701 interrupt pin goes LOW and stays LOW when an

interrupt event has occurred, as defined by the SCOM command. The interrupt is cleared when a

RINT (read interrupt) command is executed. The status register defines what type of interrupt has

occurred.

R/ B (Ready/Busy Signal)

The R/ B line is an output open drain pin used to control data transfer rate across the SPI port. The

line is used as a handshake signal to the SPI Master to indicate when the device is ready for more

data. When HIGH, the master is free to send more data. When LOW, the device is busy and cannot

accept more data.

7.2.6 The CODEC Interface

The WTS701 provides an on chip interface for digital environment systems, supporting slave CODEC

interface mode. The WTS701 CODEC interface is controlled by an external source hence the

WTS701 only transmits data. Thus, it is effectively an analog-to-digital converter. Each analog sample

is converted to 10 bit digital word. This digital word is transmitted with the MSB first. Since the host

expects either 13 or 16 bit data in the short frame format, either three or six zeros are appended as

the LSB. It interfaces to the baseband CODEC via the VCLK, VFS and VDX lines. Refer to Figure 2,

for more information about the connection between the WTS701 and a CODEC.

All Input pins are 3V and 5V tolerant.

The following is a description of the WTS701 CODEC interface signals:

VCLK (CODEC Clock Line)

The CODEC clock line supplies the sampling clock to the internal CODEC. This is a digital input and

expects a 512kHz—2.048MHz clock.

WTS701MF/T Datasheet(PDF) 16 Page - Winbond