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SPC563M64L7 Datasheet(PDF) 17 Page - STMicroelectronics |
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SPC563M64L7 Datasheet(HTML) 17 Page - STMicroelectronics |
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17 / 48 page ![]() SPC563Mxx Device overview Doc ID 13850 Rev 6 17/48 angle. – Priority Based CFIFOs Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served first. Supports software and several hardware trigger modes to arm a particular CFIFO Generates interrupt when command coherency is not achieved – External Hardware Triggers Supports rising edge, falling edge, high level and low level triggers Supports configurable digital filter – Supports four external 8-to-1 muxes which can expand the input channel number from 34(d) to 59 ● Two deserial serial peripheral interface modules (DSPI) –SPI Full duplex communication ports with interrupt and DMA request support Support for queues in RAM 6 chip selects, expandable to 64 with external demultiplexers Programmable frame size, baud rate, clock delay and clock phase on a per frame basis Modified SPI mode for interfacing to peripherals with longer setup time requirements LVDS option for output clock and data to allow higher speed communication – Deserial serial interface (DSI) Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO 32 bits per DSPI module Triggered transfer control and change in data transfer control (for reduced EMI) Compatible with Microsecond Channel Version 1.0 downstream ● Two enhanced serial communication interface (eSCI) modules – UART mode provides NRZ format and half or full duplex interface – eSCI bit rate up to 1 Mbps – Advanced error detection, and optional parity generation and detection – Word length programmable as 8, 9, 12 or 13 bits – Separately enabled transmitter and receiver – LIN support – DMA support – Interrupt request support – Programmable clock source: system clock or oscillator clock – Support Microsecond Channel (Timed Serial Bus - TSB) upstream Version 1.0 ● Two FlexCAN d. 176-pin and 208-ball packages. |
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