SPC563M64L7 datasheet(41/48 Pages) STMICROELECTRONICS

41 / 48 page

SPC563Mxx

Device overview

Doc ID 13850 Rev 6

41/48

Note:

This feature is imprecise due to CPU pipelining.

–

Subset of Power Architecture software debug facilities with OnCE block (Nexus

class 1 features)

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eTPU development support features

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IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU

–

Nexus based breakpoint configuration and single step support (JTAG feature of

the eTPU)

●

Run-time access to the on-chip memory map via the Nexus read/write access protocol.

This feature supports accesses for run-time internal visibility, calibration variable

acquisition, calibration constant tuning, and external rapid prototyping for powertrain

automotive development systems.

●

All features are independently configurable and controllable via the IEEE 1149.1 I/O

port

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Power-on-reset status indication during reset via MDO[0] in disabled and reset modes

JTAG

The JTAGC (JTAG Controller) block provides the means to test chip functionality and

connectivity while remaining transparent to system logic when not in test mode. Testing is

performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All

data input to and output from the JTAGC block is communicated in serial format. The JTAGC

block is compliant with the IEEE 1149.1-2001 standard and supports the following features:

●

IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)

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A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

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BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP

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A 5-bit instruction register that supports the additional following public instructions:

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ACCESS_AUX_TAP_NPC

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ACCESS_AUX_TAP_ONCE

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ACCESS_AUX_TAP_eTPU

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ACCESS_CENSOR

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3 test data registers to support JTAG Boundary Scan mode

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Bypass register

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Boundary scan register

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Device identification register

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A TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry

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Censorship Inhibit Register

–

64-bit Censorship password register

–

If the external tool writes a 64-bit password that matches the Serial Boot password

stored in the internal flash shadow row, Censorship is disabled until the next

system reset.

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