SPC563M64L7 datasheet(30/48 Pages) STMICROELECTRONICS

30 / 48 page

Device overview

SPC563Mxx

30/48

Doc ID 13850 Rev 6

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Event-triggered microengine:

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Fixed-length instruction execution in two-system-clock microcycle

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14 KB of code memory (SCM)

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3 KB of parameter (data) RAM (SPRAM)

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Parallel execution of data memory, ALU, channel control and flow control sub-

instructions in selected combinations

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32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and

subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte

operands, single-bit manipulation, shift operations, sign extension and conditional

execution

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Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned

Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit

works in parallel with the regular microcode commands

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Resource sharing features support channel use of common channel registers, memory

and microengine time:

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Hardware scheduler works as a “task management” unit, dispatching event

service routines by predefined, host-configured priority

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Automatic channel context switch when a “task switch” occurs, i.e., one function

thread ends and another begins to service a request from other channel: channel-

specific registers, flags and parameter base address are automatically loaded for

the next serviced channel

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SPRAM shared between host CPU and eTPU2, supporting communication either

between channels and host or inter-channel

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Dual-parameter coherency hardware support allows atomic access to two

parameters by host

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Test and development support features:

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Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction

execution, hardware breakpoints and watchpoints on several conditions

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Software breakpoints

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SCM continuous signature-check built-in self test (MISC — multiple input

signature calculator), runs concurrently with eTPU2 normal operation

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System enhancements

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Software watchdog with programmable timeout

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Real-time performance information

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Channel enhancements

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Channels 1 and 2 can optionally drive angle clock hardware

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Programming enhancements

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Engine relative addressing mode

3.3.14

eQADC

The enhanced queued analog to digital converter (eQADC) block provides accurate and fast

conversions for a wide range of applications. The eQADC provides a parallel interface to two

on-chip analog to digital converters (ADC), and a single master to single slave serial

interface to an off-chip external device. Both on-chip ADCs have access to all the analog

channels.

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