SPC563M64L7 datasheet(38/48 Pages) STMICROELECTRONICS

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Device overview

SPC563Mxx

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Doc ID 13850 Rev 6

clocked by the crystal clock. This one channel is also referred to as Real Time Interrupt

(RTI) and is used to wakeup the device from low power stop mode.

The following features are implemented in the PIT:

●

5 independent timer channels

●

Each channel includes 32-bit wide down counter with automatic reload

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4 channels clocked from system clock

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1 channel clocked from crystal clock (wake-up timer)

●

Wake-up timer remains active when System STOP mode is entered. Used to restart

system clock after predefined time-out period

●

Each channel can optionally generate an interrupt request or a trigger event (to trigger

eQADC queues) when the timer reaches zero

System Timer Module (STM)

The System Timer Module (STM) is designed to implement the software task monitor as

defined by AUTOSAR (see http://www.autosar.org). It consists of a single 32-bit counter,

clocked by the system clock, and four independent timer comparators. These comparators

produce a CPU interrupt when the timer exceeds the programmed value.

The following features are implemented in the STM:

●

One 32-bit up counter with 8-bit prescaler

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Four 32-bit compare channels

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Independent interrupt source for each channel

●

Counter can be stopped in debug mode

3.3.19

Software Watchdog Timer (SWT)

The Software Watchdog Timer (SWT) is a second watchdog module to complement the

standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit

modulus counter, clocked by the system clock or the crystal clock, that can provide a system

reset or interrupt request when the correct software key is not written within the required

time window.

The following features are implemented:

●

32-bit modulus counter

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Clocked by system clock or crystal clock

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Optional programmable watchdog window mode

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Can optionally cause system reset or interrupt request on timeout

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Reset by writing a software key to memory mapped register

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Enabled out of reset

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Configuration is protected by a software key or a write-once register

3.3.20

Debug features

Nexus port controller

The NPC (Nexus Port Controller) block provides real-time development support capabilities

for the SPC563Mxx Power Architecture-based MCU in compliance with the IEEE-ISTO

5001-2003 standard. This development support is supplied for MCUs without requiring

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