Bit select

Description

7

not used

6

Selection for fill-and-spill: all odd pixels

5

Selection for fill-and-spill: pixels 2, 6, 10 etc.

4

Selection for fill-and-spill: pixels 4, 12, 20 etc

3

Selection for fill-and-spill: pixels 0, 8, 16 etc.

2:0

NUM_FILL_SPILL_CYC

Table 32: Bit select description of register ANA_TEST_CONF in fill-and-spill test mode

Fill-and-spill procedure:

1. Force the chip into test mode by applying the following voltages:

TEST_MODE = VDD

ROI_SEL = 0V or VDD

RD_DIR = 0V or VDD

2. Open the access to the test mode configuration registers by the following two write operations. The two accesses must occur as a se -

quence, no other read or write access is allowed in between them in order to enable writing to the test registers. Once enabled, the

write access remains available until the next time the IC is reset.

ANA_TEST_MODE_EN_0: 0x4A

ANA_TEST_MODE_EN_1: 0x66

3. Configure IC into fill-and-spill test mode by the following write access

ANA_TEST_CTRL: 0x02

ANA_TEST_MUX_0_SEL: 0x20

ANA_TEST_MUX_1_SEL: 0x21

5. Configure the number of fill-and-spill cycles and select the pattern of pixels to be stimulated by writing to register ANA_TEST_CONF

(see Table 32)

7. Wait for 10 µs

8. Acquire a frame by operating the SHUTTER input as described in section 5.5. and Figure 19.

9. Read-out the frame as described in section 5.4.

10. Disconnect external voltage sources from pads ANA_TEST_*

11. Configure test mode registers to their initial values

ANA_TEST_MUX_0_SEL: 0x00

ANA_TEST_MUX_1_SEL: 0x01

ANA_TEST_CTRL: 0x0

ANA_TEST_CONF: 0x0

12. Leave test mode by applying the following voltages:

TEST_MODE = 0V

ROI_SEL → application dependent

RD_DIR → application dependent

15.1. Important notes to fill-and-spill

■ In test mode the IC can behave in an unexpected way if the procedure described above is not strictly followed.

the theoretical value. In addition to that, the voltage will vary over the pixel field.

when the IC is in fill-and-spill test mode. Otherwise, the chip can get damaged!

© 2016 ESPROS Photonics Corporation

Characteristics subject to change without notice

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Datasheet_epc901-V5.6

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