6. Temperature sensor

There are two temperature sensors on the IC, one on each side of the pixel array. They are turned off by default and can be turned on

ration can take place during manufacturing of the system by applying one or two reference temperature/s and storing the calibration value

in a non-volatile memory e.g. in the µC.

The digitized output of the temperature sensors can be read through the I2C interface registers TEMP_SENSE* (refer to Table 15 … Table

18). As soon as one of these addresses is read, the update of these registers with new temperature values is blocked until all four registers

are read. The sequence in which these registers are read, is not important.

7. Power-down mode

The chip can be forced into power-down mode to reduce the power consumption.

PWR_DOWN

Description

L

Operation

H

Power-down mode activated

If the chip is forced to power-down while frames are still stored on the IC, these frames are lost with power-down. When PWR_DOWN is

asserted during an acquisition or transmission, the current operation is finished before the chip goes to power-down. When the power-

array is it automatically flushed. In the power-down mode, no charge is collected by the CCD.

8. Chip reset

The digital control unit of the epc901 IC can be reset by the following mechanisms:

■ Disconnecting and reconnecting the power supply

■ Reset command through I2C (software reset)

9. Measuring the internal oscillator clock frequency

The epc901 chip has an internal oscillator which controls the operation of the chip. The typical frequency is approx. 35MHz but it has a

significant tolerance (refer to chapter 3.5, Timing parameters), as well as a temperature drift. To measure this frequency in order to apply

an optimized timing, the following procedure can be used:

1.

Apply CLR_DATA

2.

3.

SHUTTER

T

SHUTTER

T

MEAS

DATA_RDY

CLR_DATA

T

PULSE,CLR_DATA

Figure 11: Sequence to measure internal clock frequency

following formula:

E.g. if the measured time is 600ns, the oscillator frequency is between 40 and 43.3MHz. If the clock frequency shall be acquired more

clock frequency can be trimmed by setting a configuration register according to the description in Table 11 and 12.

© 2016 ESPROS Photonics Corporation

Characteristics subject to change without notice

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F

n

∗ClockCycles

T

MEAS