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R5F564MFDDFB Datasheet(PDF) 116 Page - Renesas Technology Corp |
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R5F564MFDDFB Datasheet(HTML) 116 Page - Renesas Technology Corp |
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116 / 228 page  R01DS0173EJ0110 Rev.1.10 Page 116 of 228 Oct 24, 2016 RX64M Group 4. I/O Registers 000C 0050h EDMAC 0 FIFO Depth Register FDR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 0058h EDMAC 0 Receive Method Control Register RMCR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 0064h EDMAC 0 Transmit FIFO Underflow Counter TFUCR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 0068h EDMAC 0 Receive FIFO Overflow Counter RFOCR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 006Ch EDMAC 0 Independent Output Signal Setting Register IOSR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 0070h EDMAC 0 Flow Control Start FIFO Threshold Setting Register FCFTR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 0078h EDMAC 0 Receive Data Padding Insert Register RPADIR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 007Ch EDMAC 0 Transmit Interrupt Setting Register TRIMD 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 00C8h EDMAC 0 Receive Buffer Write Address Register RBWAR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 00CCh EDMAC 0 Receive Descriptor Fetch Address Register RDFAR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 00D4h EDMAC 0 Transmit Buffer Read Address Register TBRAR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 00D8h EDMAC 0 Transmit Descriptor Fetch Address Register TDFAR 32 32 4, 5 PCLKA 2, 3 ICLK EDMAC a 000C 0100h ETHER C0 ETHERC Mode Register ECMR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0108h ETHER C0 Receive Frame Maximum Length Register RFLR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0110h ETHER C0 ETHERC Status Register ECSR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0118h ETHER C0 ETHERC Interrupt Enable Register ECSIPR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0120h ETHER C0 PHY Interface Register PIR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0128h ETHER C0 PHY Status Register PSR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0140h ETHER C0 Random Number Generation Counter Limit Setting Register RDMLR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0150h ETHER C0 Interpacket Gap Register IPGR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0154h ETHER C0 Automatic PAUSE Frame Register APR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0158h ETHER C0 Manual PAUSE Frame Register MPR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0160h ETHER C0 Received PAUSE Frame Counter RFCF 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0164h ETHER C0 PAUSE Frame Retransmit Count Setting Register TPAUSER 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 0168h ETHER C0 PAUSE Frame Retransmit Counter TPAUSECR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 016Ch ETHER C0 Broadcast Frame Receive Count Setting Register BCFRR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 01C0h ETHER C0 MAC Address Upper Bit Register MAHR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 01C8h ETHER C0 MAC Address Lower Bit Register MALR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 01D0h ETHER C0 Transmit Retry Over Counter Register TROCR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 01D4h ETHER C0 Late Collision Detect Counter Register CDCR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C 000C 01D8h ETHER C0 Lost Carrier Counter Register LCCR 32 32 13, 14 PCLKA 2 to 7 ICLK ETHER C Table 4.1 List of I/O Registers (Address Order) (45 / 67) Address Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access Cycles Related Function ICLK PCLK ICLK PCLK |
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